/* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License * Version 2 or later at the following locations: * * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ /include/ "skeleton.dtsi" / { aliases { serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; gpio5 = &gpio6; gpio6 = &gpio7; }; tzic: tz-interrupt-controller@0fffc000 { compatible = "fsl,imx53-tzic", "fsl,tzic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x0fffc000 0x4000>; }; clocks { #address-cells = <1>; #size-cells = <0>; ckil { compatible = "fsl,imx-ckil", "fixed-clock"; clock-frequency = <32768>; }; ckih1 { compatible = "fsl,imx-ckih1", "fixed-clock"; clock-frequency = <22579200>; }; ckih2 { compatible = "fsl,imx-ckih2", "fixed-clock"; clock-frequency = <0>; }; osc { compatible = "fsl,imx-osc", "fixed-clock"; clock-frequency = <24000000>; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&tzic>; ranges; aips@50000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x50000000 0x10000000>; ranges; spba@50000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x50000000 0x40000>; ranges; esdhc@50004000 { /* ESDHC1 */ compatible = "fsl,imx53-esdhc"; reg = <0x50004000 0x4000>; interrupts = <1>; status = "disabled"; }; esdhc@50008000 { /* ESDHC2 */ compatible = "fsl,imx53-esdhc"; reg = <0x50008000 0x4000>; interrupts = <2>; status = "disabled"; }; uart3: serial@5000c000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; interrupts = <33>; status = "disabled"; }; ecspi@50010000 { /* ECSPI1 */ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x50010000 0x4000>; interrupts = <36>; status = "disabled"; }; ssi2: ssi@50014000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <30>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; esdhc@50020000 { /* ESDHC3 */ compatible = "fsl,imx53-esdhc"; reg = <0x50020000 0x4000>; interrupts = <3>; status = "disabled"; }; esdhc@50024000 { /* ESDHC4 */ compatible = "fsl,imx53-esdhc"; reg = <0x50024000 0x4000>; interrupts = <4>; status = "disabled"; }; }; usb@53f80000 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; status = "disabled"; }; usb@53f80200 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80200 0x0200>; interrupts = <14>; status = "disabled"; }; usb@53f80400 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80400 0x0200>; interrupts = <16>; status = "disabled"; }; usb@53f80600 { compatible = "fsl,imx53-usb", "fsl,imx27-usb"; reg = <0x53f80600 0x0200>; interrupts = <17>; status = "disabled"; }; gpio1: gpio@53f84000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; interrupts = <50 51>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@53f88000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f88000 0x4000>; interrupts = <52 53>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@53f8c000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f8c000 0x4000>; interrupts = <54 55>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@53f90000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53f90000 0x4000>; interrupts = <56 57>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; wdog@53f98000 { /* WDOG1 */ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; }; wdog@53f9c000 { /* WDOG2 */ compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; status = "disabled"; }; iomuxc@53fa8000 { compatible = "fsl,imx53-iomuxc"; reg = <0x53fa8000 0x4000>; audmux { pinctrl_audmux_1: audmuxgrp-1 { fsl,pins = < 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ >; }; }; fec { pinctrl_fec_1: fecgrp-1 { fsl,pins = < 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ >; }; }; ecspi1 { pinctrl_ecspi1_1: ecspi1grp-1 { fsl,pins = < 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ >; }; }; esdhc1 { pinctrl_esdhc1_1: esdhc1grp-1 { fsl,pins = < 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ >; }; pinctrl_esdhc1_2: esdhc1grp-2 { fsl,pins = < 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ >; }; }; esdhc2 { pinctrl_esdhc2_1: esdhc2grp-1 { fsl,pins = < 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ >; }; }; esdhc3 { pinctrl_esdhc3_1: esdhc3grp-1 { fsl,pins = < 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ >; }; }; i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = < 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ >; }; }; i2c2 { pinctrl_i2c2_1: i2c2grp-1 { fsl,pins = < 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ >; }; }; uart1 { pinctrl_uart1_1: uart1grp-1 { fsl,pins = < 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ >; }; pinctrl_uart1_2: uart1grp-2 { fsl,pins = < 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ >; }; }; uart2 { pinctrl_uart2_1: uart2grp-1 { fsl,pins = < 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ >; }; }; uart3 { pinctrl_uart3_1: uart3grp-1 { fsl,pins = < 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ >; }; }; }; uart1: serial@53fbc000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fbc000 0x4000>; interrupts = <31>; status = "disabled"; }; uart2: serial@53fc0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53fc0000 0x4000>; interrupts = <32>; status = "disabled"; }; can1: can@53fc8000 { compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fc8000 0x4000>; interrupts = <82>; status = "disabled"; }; can2: can@53fcc000 { compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; reg = <0x53fcc000 0x4000>; interrupts = <83>; status = "disabled"; }; gpio5: gpio@53fdc000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fdc000 0x4000>; interrupts = <103 104>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio6: gpio@53fe0000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fe0000 0x4000>; interrupts = <105 106>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio7: gpio@53fe4000 { compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; reg = <0x53fe4000 0x4000>; interrupts = <107 108>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; i2c@53fec000 { /* I2C3 */ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x53fec000 0x4000>; interrupts = <64>; status = "disabled"; }; uart4: serial@53ff0000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x53ff0000 0x4000>; interrupts = <13>; status = "disabled"; }; }; aips@60000000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x60000000 0x10000000>; ranges; uart5: serial@63f90000 { compatible = "fsl,imx53-uart", "fsl,imx21-uart"; reg = <0x63f90000 0x4000>; interrupts = <86>; status = "disabled"; }; ecspi@63fac000 { /* ECSPI2 */ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; reg = <0x63fac000 0x4000>; interrupts = <37>; status = "disabled"; }; sdma@63fb0000 { compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; reg = <0x63fb0000 0x4000>; interrupts = <6>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; }; cspi@63fc0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; reg = <0x63fc0000 0x4000>; interrupts = <38>; status = "disabled"; }; i2c@63fc4000 { /* I2C2 */ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc4000 0x4000>; interrupts = <63>; status = "disabled"; }; i2c@63fc8000 { /* I2C1 */ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; reg = <0x63fc8000 0x4000>; interrupts = <62>; status = "disabled"; }; ssi1: ssi@63fcc000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; interrupts = <29>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; audmux@63fd0000 { compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; reg = <0x63fd0000 0x4000>; status = "disabled"; }; nand@63fdb000 { compatible = "fsl,imx53-nand"; reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; interrupts = <8>; status = "disabled"; }; ssi3: ssi@63fe8000 { compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; interrupts = <96>; fsl,fifo-depth = <15>; fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ status = "disabled"; }; ethernet@63fec000 { compatible = "fsl,imx53-fec", "fsl,imx25-fec"; reg = <0x63fec000 0x4000>; interrupts = <87>; status = "disabled"; }; }; }; };