/*
 *  Copyright (C) 2011 Xilinx
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;
/ {
	model = "Xilinx Zynq EP107";
	compatible = "xlnx,zynq-ep107";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;

	memory {
		device_type = "memory";
		reg = <0x0 0x10000000>;
	};

	chosen {
		bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
		linux,stdout-path = &uart0;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		intc: interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xF8F01000 0x1000>,
			      <0xF8F00100 0x100>;
		};

		L2: cache-controller {
			compatible = "arm,pl310-cache";
			reg = <0xF8F02000 0x1000>;
			arm,data-latency = <2 3 2>;
			arm,tag-latency = <2 3 2>;
			cache-unified;
			cache-level = <2>;
		};

		uart0: uart@e0000000 {
			compatible = "xlnx,xuartps";
			reg = <0xE0000000 0x1000>;
			interrupts = <0 27 4>;
			clock = <50000000>;
		};
	};
};