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* Device tree bindings for Texas Instruments keystone reset
This node is intended to allow SoC reset in case of software reset
of selected watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux
block. The Reset Mux block can be configured to cause reset or not.
Additionally soft or hard reset can be configured.
Required properties:
- compatible: ti,keystone-reset
- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
access pll controller registers and the offset to use
reset control registers.
- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
access device state control registers and the offset
in order to use mux block registers for all watchdogs.
Optional properties:
- ti,soft-reset: Boolean option indicating soft reset.
By default hard reset is used.
- ti,wdt-list: WDT list that can cause SoC reset. It's not related
to WDT driver, it's just needed to enable a SoC related
reset that's triggered by one of WDTs. The list is
in format: <0>, <2>; It can be in random order and
begins from 0 to 3, as keystone can contain up to 4 SoC
reset watchdogs and can be in random order.
Example 1:
Setup keystone reset so that in case software reset or
WDT0 is triggered it issues hard reset for SoC.
pllctrl: pll-controller@02310000 {
compatible = "ti,keystone-pllctrl", "syscon";
reg = <0x02310000 0x200>;
};
devctrl: device-state-control@02620000 {
compatible = "ti,keystone-devctrl", "syscon";
reg = <0x02620000 0x1000>;
};
rstctrl: reset-controller {
compatible = "ti,keystone-reset";
ti,syscon-pll = <&pllctrl 0xe4>;
ti,syscon-dev = <&devctrl 0x328>;
ti,wdt-list = <0>;
};
Example 2:
Setup keystone reset so that in case of software reset or
WDT0 or WDT2 is triggered it issues soft reset for SoC.
rstctrl: reset-controller {
compatible = "ti,keystone-reset";
ti,syscon-pll = <&pllctrl 0xe4>;
ti,syscon-dev = <&devctrl 0x328>;
ti,wdt-list = <0>, <2>;
ti,soft-reset;
};
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