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/*
* Samsung's Exynos4212 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4212";
gic:interrupt-controller@10490000 {
cpu-offset = <0x8000>;
};
interrupt-controller@10440000 {
samsung,combiner-nr = <18>;
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
<0 107 0>, <0 108 0>;
};
mct@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
interrupt-controller;
#interrups-cells = <2>;
interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>;
mct_map: mct-map {
#interrupt-cells = <2>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = <0x0 0 &gic 0 57 0>,
<0x1 0 &combiner 12 5>,
<0x2 0 &combiner 12 6>,
<0x3 0 &combiner 12 7>,
<0x4 0 &gic 1 12 0>,
<0x5 0 &gic 1 12 0>;
};
};
};
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