1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
};
tzic: tz-interrupt-controller@0fffc000 {
compatible = "fsl,imx53-tzic", "fsl,tzic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x0fffc000 0x4000>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
ipu: ipu@18000000 {
#crtc-cells = <1>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
interrupts = <11 10>;
};
aips@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x10000000>;
ranges;
spba@50000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x40000>;
ranges;
esdhc1: esdhc@50004000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50004000 0x4000>;
interrupts = <1>;
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc2: esdhc@50008000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50008000 0x4000>;
interrupts = <2>;
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
uart3: serial@5000c000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x5000c000 0x4000>;
interrupts = <33>;
clocks = <&clks 32>, <&clks 33>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi1: ecspi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks 51>, <&clks 52>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi2: ssi@50014000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
reg = <0x50014000 0x4000>;
interrupts = <30>;
clocks = <&clks 49>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
esdhc3: esdhc@50020000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50020000 0x4000>;
interrupts = <3>;
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc4: esdhc@50024000 {
compatible = "fsl,imx53-esdhc";
reg = <0x50024000 0x4000>;
interrupts = <4>;
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
usbotg: usb@53f80000 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
usbh1: usb@53f80200 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
usbh2: usb@53f80400 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
usbh3: usb@53f80600 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
status = "disabled";
};
gpio1: gpio@53f84000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@53f88000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f88000 0x4000>;
interrupts = <52 53>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@53f8c000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f8c000 0x4000>;
interrupts = <54 55>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@53f90000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f90000 0x4000>;
interrupts = <56 57>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
wdog1: wdog@53f98000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
clocks = <&clks 0>;
};
wdog2: wdog@53f9c000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f9c000 0x4000>;
interrupts = <59>;
clocks = <&clks 0>;
status = "disabled";
};
iomuxc: iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
>;
};
pinctrl_esdhc1_2: esdhc1grp-2 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
>;
};
};
esdhc3 {
pinctrl_esdhc3_1: esdhc3grp-1 {
fsl,pins = <
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
>;
};
};
can1 {
pinctrl_can1_1: can1grp-1 {
fsl,pins = <
847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
>;
};
};
can2 {
pinctrl_can2_1: can2grp-1 {
fsl,pins = <
67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
>;
};
};
i2c3 {
pinctrl_i2c3_1: i2c3grp-1 {
fsl,pins = <
1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
>;
};
};
uart5 {
pinctrl_uart5_1: uart5grp-1 {
fsl,pins = <
24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
>;
};
};
};
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
clocks = <&clks 37>, <&clks 38>;
clock-names = "ipg", "per";
interrupts = <61>;
};
pwm2: pwm@53fb8000 {
#pwm-cells = <2>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb8000 0x4000>;
clocks = <&clks 39>, <&clks 40>;
clock-names = "ipg", "per";
interrupts = <94>;
};
uart1: serial@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks 28>, <&clks 29>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@53fc0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks 30>, <&clks 31>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
clocks = <&clks 158>, <&clks 157>;
clock-names = "ipg", "per";
status = "disabled";
};
can2: can@53fcc000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
clocks = <&clks 87>, <&clks 86>;
clock-names = "ipg", "per";
status = "disabled";
};
clks: ccm@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
#clock-cells = <1>;
};
gpio5: gpio@53fdc000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fdc000 0x4000>;
interrupts = <103 104>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@53fe0000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fe0000 0x4000>;
interrupts = <105 106>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@53fe4000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fe4000 0x4000>;
interrupts = <107 108>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c3: i2c@53fec000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
reg = <0x53fec000 0x4000>;
interrupts = <64>;
clocks = <&clks 88>;
status = "disabled";
};
uart4: serial@53ff0000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53ff0000 0x4000>;
interrupts = <13>;
clocks = <&clks 65>, <&clks 66>;
clock-names = "ipg", "per";
status = "disabled";
};
};
aips@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x60000000 0x10000000>;
ranges;
uart5: serial@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
interrupts = <86>;
clocks = <&clks 67>, <&clks 68>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@63fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks 53>, <&clks 54>;
clock-names = "ipg", "per";
status = "disabled";
};
sdma: sdma@63fb0000 {
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks 56>, <&clks 56>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
cspi: cspi@63fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
reg = <0x63fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks 55>, <&clks 0>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c2: i2c@63fc4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
reg = <0x63fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks 35>;
status = "disabled";
};
i2c1: i2c@63fc8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
reg = <0x63fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks 34>;
status = "disabled";
};
ssi1: ssi@63fcc000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
reg = <0x63fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks 48>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
audmux: audmux@63fd0000 {
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
reg = <0x63fd0000 0x4000>;
status = "disabled";
};
nfc: nand@63fdb000 {
compatible = "fsl,imx53-nand";
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
interrupts = <8>;
clocks = <&clks 60>;
status = "disabled";
};
ssi3: ssi@63fe8000 {
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
reg = <0x63fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks 50>;
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
};
fec: ethernet@63fec000 {
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
reg = <0x63fec000 0x4000>;
interrupts = <87>;
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
};
};
};
|
