summaryrefslogtreecommitdiffstats
path: root/arch/mips/pci/ops-marvell.c
blob: 1ac5c59199d1b9f18c890a621672ce218468bfe7 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>

#include <asm/marvell.h>

static int mv_read_config(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 * val)
{
	struct mv_pci_controller *mvbc = bus->sysdata;
	unsigned long address_reg, data_reg;
	u32 address;

	address_reg = mvbc->config_addr;
	data_reg = mvbc->config_vreg;

	/* Accessing device 31 crashes those Marvells.  Since years.
	   Will they ever make sane controllers ... */
	if (PCI_SLOT(devfn) == 31)
		return PCIBIOS_DEVICE_NOT_FOUND;

	address = (bus->number << 16) | (devfn << 8) |
	          (where & 0xfc) | 0x80000000;

	/* start the configuration cycle */
	MV_WRITE(address_reg, address);

	switch (size) {
	case 1:
		*val = MV_READ_8(data_reg + (where & 0x3));
		break;

	case 2:
		*val = MV_READ_16(data_reg + (where & 0x3));
		break;

	case 4:
		*val = MV_READ(data_reg);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int mv_write_config(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 val)
{
	struct mv_pci_controller *mvbc = bus->sysdata;
	unsigned long address_reg, data_reg;
	u32 address;

	address_reg = mvbc->config_addr;
	data_reg = mvbc->config_vreg;

	/* Accessing device 31 crashes those Marvells.  Since years.
	   Will they ever make sane controllers ... */
	if (PCI_SLOT(devfn) == 31)
		return PCIBIOS_DEVICE_NOT_FOUND;

	address = (bus->number << 16) | (devfn << 8) |
	          (where & 0xfc) | 0x80000000;

	/* start the configuration cycle */
	MV_WRITE(address_reg, address);

	switch (size) {
	case 1:
		MV_WRITE_8(data_reg + (where & 0x3), val);
		break;

	case 2:
		MV_WRITE_16(data_reg + (where & 0x3), val);
		break;

	case 4:
		MV_WRITE(data_reg, val);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

struct pci_ops mv_pci_ops = {
	.read	= mv_read_config,
	.write	= mv_write_config
};