1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
|
/*
* MPC8323E EMDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
* this:
*
* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
* next to the serial ports.
* 3) Solder a wire from U61-22 to P19K-22.
*
* Note that there's a typo in the schematic. The board labels the last column
* of pins "P19K", but in the schematic, that column is called "P19J". So if
* you're going by the schematic, the pin is called "P19J-K22".
*/
/ {
model = "MPC8323EMDS";
compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8323@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <4000>; // L1, 16K
i-cache-size = <4000>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <00000000 08000000>;
};
bcsr@f8000000 {
device_type = "board-control";
reg = <f8000000 8000>;
};
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <7DE2900>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <200 100>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <e 8>;
interrupt-parent = < &ipic >;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <68>;
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <9 8>;
interrupt-parent = < &ipic >;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <a 8>;
interrupt-parent = < &ipic >;
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 7000>;
interrupts = <b 8>;
interrupt-parent = < &ipic >;
/* Rev. 2.2 */
num-channels = <1>;
channel-fifo-len = <18>;
exec-units-mask = <0000004c>;
descriptor-types-mask = <0122003f>;
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
par_io@1400 {
reg = <1400 100>;
device_type = "par_io";
num-ports = <7>;
pio3: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
0 d 2 0 1 0 /* RX_CLK (CLK9) */
3 18 2 0 1 0 /* TX_CLK (CLK10) */
1 0 1 0 1 0 /* TxD0 */
1 1 1 0 1 0 /* TxD1 */
1 2 1 0 1 0 /* TxD2 */
1 3 1 0 1 0 /* TxD3 */
1 4 2 0 1 0 /* RxD0 */
1 5 2 0 1 0 /* RxD1 */
1 6 2 0 1 0 /* RxD2 */
1 7 2 0 1 0 /* RxD3 */
1 8 2 0 1 0 /* RX_ER */
1 9 1 0 1 0 /* TX_ER */
1 a 2 0 1 0 /* RX_DV */
1 b 2 0 1 0 /* COL */
1 c 1 0 1 0 /* TX_EN */
1 d 2 0 1 0>;/* CRS */
};
pio4: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 1f 2 0 1 0 /* RX_CLK (CLK7) */
3 6 2 0 1 0 /* TX_CLK (CLK8) */
1 12 1 0 1 0 /* TxD0 */
1 13 1 0 1 0 /* TxD1 */
1 14 1 0 1 0 /* TxD2 */
1 15 1 0 1 0 /* TxD3 */
1 16 2 0 1 0 /* RxD0 */
1 17 2 0 1 0 /* RxD1 */
1 18 2 0 1 0 /* RxD2 */
1 19 2 0 1 0 /* RxD3 */
1 1a 2 0 1 0 /* RX_ER */
1 1b 1 0 1 0 /* TX_ER */
1 1c 2 0 1 0 /* RX_DV */
1 1d 2 0 1 0 /* COL */
1 1e 1 0 1 0 /* TX_EN */
1 1f 2 0 1 0>;/* CRS */
};
pio5: ucc_pin@05 {
pio-map = <
/*
* open has
* port pin dir drain sel irq
*/
2 0 1 0 2 0 /* TxD5 */
2 8 2 0 2 0 /* RxD5 */
2 1d 2 0 0 0 /* CTS5 */
2 1f 1 0 2 0 /* RTS5 */
2 18 2 0 0 0 /* CD */
>;
};
};
};
qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0 e0100000 00100000>;
reg = <e0100000 480>;
brg-frequency = <0>;
bus-frequency = <BCD3D80>;
muram@10000 {
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 00010000 00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0 4000>;
};
};
spi@4c0 {
device_type = "spi";
compatible = "fsl_spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = < &qeic >;
mode = "cpu";
};
spi@500 {
device_type = "spi";
compatible = "fsl_spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = < &qeic >;
mode = "cpu";
};
usb@6c0 {
compatible = "qe_udc";
reg = <6c0 40 8B00 100>;
interrupts = <b>;
interrupt-parent = < &qeic >;
mode = "slave";
};
enet0: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <3>;
device-id = <3>;
reg = <2200 200>;
interrupts = <22>;
interrupt-parent = < &qeic >;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk9";
tx-clock-name = "clk10";
phy-handle = < &phy3 >;
pio-handle = < &pio3 >;
};
enet1: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <4>;
device-id = <4>;
reg = <3200 200>;
interrupts = <23>;
interrupt-parent = < &qeic >;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk7";
tx-clock-name = "clk8";
phy-handle = < &phy4 >;
pio-handle = < &pio4 >;
};
ucc@2400 {
device_type = "serial";
compatible = "ucc_uart";
model = "UCC";
device-id = <5>; /* The UCC number, 1-7*/
port-number = <0>; /* Which ttyQEx device */
soft-uart; /* We need Soft-UART */
reg = <2400 200>;
interrupts = <28>; /* From Table 18-12 */
interrupt-parent = < &qeic >;
/*
* For Soft-UART, we need to set TX to 1X, which
* means specifying separate clock sources.
*/
rx-clock-name = "brg5";
tx-clock-name = "brg6";
pio-handle = < &pio5 >;
};
mdio@2320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2320 18>;
device_type = "mdio";
compatible = "ucc_geth_phy";
phy3: ethernet-phy@03 {
interrupt-parent = < &ipic >;
interrupts = <11 8>;
reg = <3>;
device_type = "ethernet-phy";
};
phy4: ethernet-phy@04 {
interrupt-parent = < &ipic >;
interrupts = <12 8>;
reg = <4>;
device_type = "ethernet-phy";
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = < &ipic >;
};
};
pci0: pci@e0008500 {
cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 AD18 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 AD19 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 AD21*/
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 AD22*/
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 AD23*/
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 AD24*/
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 d0000000 0 00100000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
|
