1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
|
/*
* MPC8349E MDS Device Tree Source
*
* Copyright 2005, 2006 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "MPC8349EMDS";
compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8349@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <00000000 10000000>; // 256MB at 0
};
bcsr@e2400000 {
device_type = "board-control";
reg = <e2400000 8000>;
};
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <200 100>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <e 8>;
interrupt-parent = < &ipic >;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <3100 100>;
interrupts = <f 8>;
interrupt-parent = < &ipic >;
dfsrr;
};
spi@7000 {
device_type = "spi";
compatible = "fsl_spi";
reg = <7000 1000>;
interrupts = <10 8>;
interrupt-parent = < &ipic >;
mode = "cpu";
};
/* phy type (ULPI or SERIAL) are only types supportted for MPH */
/* port = 0 or 1 */
usb@22000 {
device_type = "usb";
compatible = "fsl-usb2-mph";
reg = <22000 1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = < &ipic >;
interrupts = <27 8>;
phy_type = "ulpi";
port1;
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
device_type = "usb";
compatible = "fsl-usb2-dr";
reg = <23000 1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = < &ipic >;
interrupts = <26 8>;
dr_mode = "otg";
phy_type = "ulpi";
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <24520 20>;
phy0: ethernet-phy@0 {
interrupt-parent = < &ipic >;
interrupts = <11 8>;
reg = <0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupt-parent = < &ipic >;
interrupts = <12 8>;
reg = <1>;
device_type = "ethernet-phy";
};
};
enet0: ethernet@24000 {
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8 21 8 22 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy0 >;
linux,network-index = <0>;
};
enet1: ethernet@25000 {
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <23 8 24 8 25 8>;
interrupt-parent = < &ipic >;
phy-handle = < &phy1 >;
linux,network-index = <1>;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <9 8>;
interrupt-parent = < &ipic >;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <a 8>;
interrupt-parent = < &ipic >;
};
/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 10000>;
interrupts = <b 8>;
interrupt-parent = < &ipic >;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
/* desc mask is for rev2.0,
* we need runtime fixup for >2.0 */
descriptor-types-mask = <01010ebf>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
};
pci@e0008500 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 */
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 */
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 */
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 */
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 90000000 90000000 0 10000000
42000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci@e0008600 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
8800 0 0 1 &ipic 14 8
8800 0 0 2 &ipic 15 8
8800 0 0 3 &ipic 16 8
8800 0 0 4 &ipic 17 8
/* IDSEL 0x12 */
9000 0 0 1 &ipic 16 8
9000 0 0 2 &ipic 17 8
9000 0 0 3 &ipic 14 8
9000 0 0 4 &ipic 15 8
/* IDSEL 0x13 */
9800 0 0 1 &ipic 17 8
9800 0 0 2 &ipic 14 8
9800 0 0 3 &ipic 15 8
9800 0 0 4 &ipic 16 8
/* IDSEL 0x15 */
a800 0 0 1 &ipic 14 8
a800 0 0 2 &ipic 15 8
a800 0 0 3 &ipic 16 8
a800 0 0 4 &ipic 17 8
/* IDSEL 0x16 */
b000 0 0 1 &ipic 17 8
b000 0 0 2 &ipic 14 8
b000 0 0 3 &ipic 15 8
b000 0 0 4 &ipic 16 8
/* IDSEL 0x17 */
b800 0 0 1 &ipic 16 8
b800 0 0 2 &ipic 17 8
b800 0 0 3 &ipic 14 8
b800 0 0 4 &ipic 15 8
/* IDSEL 0x18 */
c000 0 0 1 &ipic 15 8
c000 0 0 2 &ipic 16 8
c000 0 0 3 &ipic 17 8
c000 0 0 4 &ipic 14 8>;
interrupt-parent = < &ipic >;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <02000000 0 b0000000 b0000000 0 10000000
42000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e2100000 0 00100000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008600 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};
|
