1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
|
/*
* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/oprofile.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/oprofile_impl.h>
#define dbg(args...)
static void ctrl_write(unsigned int i, unsigned int val)
{
unsigned int tmp = 0;
unsigned long shift = 0, mask = 0;
dbg("ctrl_write %d %x\n", i, val);
switch(i) {
case 0:
tmp = mfspr(SPRN_MMCR0);
shift = 6;
mask = 0x7F;
break;
case 1:
tmp = mfspr(SPRN_MMCR0);
shift = 0;
mask = 0x3F;
break;
case 2:
tmp = mfspr(SPRN_MMCR1);
shift = 31 - 4;
mask = 0x1F;
break;
case 3:
tmp = mfspr(SPRN_MMCR1);
shift = 31 - 9;
mask = 0x1F;
break;
case 4:
tmp = mfspr(SPRN_MMCR1);
shift = 31 - 14;
mask = 0x1F;
break;
case 5:
tmp = mfspr(SPRN_MMCR1);
shift = 31 - 19;
mask = 0x1F;
break;
case 6:
tmp = mfspr(SPRN_MMCR1);
shift = 31 - 24;
mask = 0x1F;
break;
case 7:
tmp = mfspr(SPRN_MMCR1);
shift = 31 - 28;
mask = 0xF;
break;
}
tmp = tmp & ~(mask << shift);
tmp |= val << shift;
switch(i) {
case 0:
case 1:
mtspr(SPRN_MMCR0, tmp);
break;
default:
mtspr(SPRN_MMCR1, tmp);
}
dbg("ctrl_write mmcr0 %lx mmcr1 %lx\n", mfspr(SPRN_MMCR0),
mfspr(SPRN_MMCR1));
}
static unsigned long reset_value[OP_MAX_COUNTER];
static int num_counters;
static void rs64_reg_setup(struct op_counter_config *ctr,
struct op_system_config *sys,
int num_ctrs)
{
int i;
num_counters = num_ctrs;
for (i = 0; i < num_counters; ++i)
reset_value[i] = 0x80000000UL - ctr[i].count;
/* XXX setup user and kernel profiling */
}
static void rs64_cpu_setup(void *unused)
{
unsigned int mmcr0;
/* reset MMCR0 and set the freeze bit */
mmcr0 = MMCR0_FC;
mtspr(SPRN_MMCR0, mmcr0);
/* reset MMCR1, MMCRA */
mtspr(SPRN_MMCR1, 0);
if (cpu_has_feature(CPU_FTR_MMCRA))
mtspr(SPRN_MMCRA, 0);
mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
/* Only applies to POWER3, but should be safe on RS64 */
mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
mtspr(SPRN_MMCR0, mmcr0);
dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
mfspr(SPRN_MMCR0));
dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
mfspr(SPRN_MMCR1));
}
static void rs64_start(struct op_counter_config *ctr)
{
int i;
unsigned int mmcr0;
/* set the PMM bit (see comment below) */
mtmsrd(mfmsr() | MSR_PMM);
for (i = 0; i < num_counters; ++i) {
if (ctr[i].enabled) {
ctr_write(i, reset_value[i]);
ctrl_write(i, ctr[i].event);
} else {
ctr_write(i, 0);
}
}
mmcr0 = mfspr(SPRN_MMCR0);
/*
* now clear the freeze bit, counting will not start until we
* rfid from this excetion, because only at that point will
* the PMM bit be cleared
*/
mmcr0 &= ~MMCR0_FC;
mtspr(SPRN_MMCR0, mmcr0);
dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
}
static void rs64_stop(void)
{
unsigned int mmcr0;
/* freeze counters */
mmcr0 = mfspr(SPRN_MMCR0);
mmcr0 |= MMCR0_FC;
mtspr(SPRN_MMCR0, mmcr0);
dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
mb();
}
static void rs64_handle_interrupt(struct pt_regs *regs,
struct op_counter_config *ctr)
{
unsigned int mmcr0;
int val;
int i;
unsigned long pc = mfspr(SPRN_SIAR);
int is_kernel = (pc >= KERNELBASE);
/* set the PMM bit (see comment below) */
mtmsrd(mfmsr() | MSR_PMM);
for (i = 0; i < num_counters; ++i) {
val = ctr_read(i);
if (val < 0) {
if (ctr[i].enabled) {
oprofile_add_pc(pc, is_kernel, i);
ctr_write(i, reset_value[i]);
} else {
ctr_write(i, 0);
}
}
}
mmcr0 = mfspr(SPRN_MMCR0);
/* reset the perfmon trigger */
mmcr0 |= MMCR0_PMXE;
/*
* now clear the freeze bit, counting will not start until we
* rfid from this exception, because only at that point will
* the PMM bit be cleared
*/
mmcr0 &= ~MMCR0_FC;
mtspr(SPRN_MMCR0, mmcr0);
}
struct op_powerpc_model op_model_rs64 = {
.reg_setup = rs64_reg_setup,
.cpu_setup = rs64_cpu_setup,
.start = rs64_start,
.stop = rs64_stop,
.handle_interrupt = rs64_handle_interrupt,
};
|
