summaryrefslogtreecommitdiffstats
path: root/arch/sh/boards/landisk/io.c
blob: aa6b145c9e8f400bbbe784bd57e66395be998f97 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
/*
 * arch/sh/boards/landisk/io.c
 *
 * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
 * Based largely on io_se.c.
 *
 * I/O routine for I-O Data Device, Inc. LANDISK.
 *
 * Initial version only to support LAN access; some
 * placeholder code from io_landisk.c left in with the
 * expectation of later SuperIO and PCMCIA access.
 */
/*
 * modifed by kogiidena
 * 2005.03.03
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/landisk/iodata_landisk.h>
#include <asm/addrspace.h>
#include <asm/io.h>

#include <linux/module.h>
#include <linux/pci.h>
#include "../../drivers/pci/pci-sh7751.h"

extern void *area5_io_base;	/* Area 5 I/O Base address */
extern void *area6_io_base;	/* Area 6 I/O Base address */

/*
 * The 7751R LANDISK uses the built-in PCI controller (PCIC)
 * of the 7751R processor, and has a SuperIO accessible via the PCI.
 * The board also includes a PCMCIA controller on its memory bus,
 * like the other Solution Engine boards.
 */

#define PCIIOBR		(volatile long *)PCI_REG(SH7751_PCIIOBR)
#define PCIMBR          (volatile long *)PCI_REG(SH7751_PCIMBR)
#define PCI_IO_AREA	SH7751_PCI_IO_BASE
#define PCI_MEM_AREA	SH7751_PCI_CONFIG_BASE

#define PCI_IOMAP(adr)	(PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK))

static inline void delay(void)
{
	ctrl_inw(0xa0000000);
}

static inline unsigned long port2adr(unsigned int port)
{
	if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
		if (port == 0x3f6)
			return ((unsigned long)area5_io_base + 0x2c);
		else
			return ((unsigned long)area5_io_base + PA_PIDE_OFFSET +
				((port - 0x1f0) << 1));
	else if ((0x170 <= port && port < 0x178) || port == 0x376)
		if (port == 0x376)
			return ((unsigned long)area6_io_base + 0x2c);
		else
			return ((unsigned long)area6_io_base + PA_SIDE_OFFSET +
				((port - 0x170) << 1));
	else
		maybebadio((unsigned long)port);

	return port;
}

/* In case someone configures the kernel w/o PCI support: in that */
/* scenario, don't ever bother to check for PCI-window addresses */

/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */
#if defined(CONFIG_PCI)
#define CHECK_SH7751_PCIIO(port) \
  ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE)))
#else
#define CHECK_SH_7751_PCIIO(port) (0)
#endif

/*
 * General outline: remap really low stuff [eventually] to SuperIO,
 * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
 * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
 * should be way beyond the window, and is used  w/o translation for
 * compatibility.
 */
u8 landisk_inb(unsigned long port)
{
	if (PXSEG(port))
		return ctrl_inb(port);
	else if (CHECK_SH7751_PCIIO(port))
		return ctrl_inb(PCI_IOMAP(port));

	return ctrl_inw(port2adr(port)) & 0xff;
}

u8 landisk_inb_p(unsigned long port)
{
	u8 v;

	if (PXSEG(port))
		v = ctrl_inb(port);
	else if (CHECK_SH7751_PCIIO(port))
		v = ctrl_inb(PCI_IOMAP(port));
	else
		v = ctrl_inw(port2adr(port)) & 0xff;

	delay();

	return v;
}

u16 landisk_inw(unsigned long port)
{
	if (PXSEG(port))
		return ctrl_inw(port);
	else if (CHECK_SH7751_PCIIO(port))
		return ctrl_inw(PCI_IOMAP(port));
	else
		maybebadio(port);

	return 0;
}

u32 landisk_inl(unsigned long port)
{
	if (PXSEG(port))
		return ctrl_inl(port);
	else if (CHECK_SH7751_PCIIO(port))
		return ctrl_inl(PCI_IOMAP(port));
	else
		maybebadio(port);

	return 0;
}

void landisk_outb(u8 value, unsigned long port)
{
	if (PXSEG(port))
		ctrl_outb(value, port);
	else if (CHECK_SH7751_PCIIO(port))
		ctrl_outb(value, PCI_IOMAP(port));
	else
		ctrl_outw(value, port2adr(port));
}

void landisk_outb_p(u8 value, unsigned long port)
{
	if (PXSEG(port))
		ctrl_outb(value, port);
	else if (CHECK_SH7751_PCIIO(port))
		ctrl_outb(value, PCI_IOMAP(port));
	else
		ctrl_outw(value, port2adr(port));
	delay();
}

void landisk_outw(u16 value, unsigned long port)
{
	if (PXSEG(port))
		ctrl_outw(value, port);
	else if (CHECK_SH7751_PCIIO(port))
		ctrl_outw(value, PCI_IOMAP(port));
	else
		maybebadio(port);
}

void landisk_outl(u32 value, unsigned long port)
{
	if (PXSEG(port))
		ctrl_outl(value, port);
	else if (CHECK_SH7751_PCIIO(port))
		ctrl_outl(value, PCI_IOMAP(port));
	else
		maybebadio(port);
}

void landisk_insb(unsigned long port, void *dst, unsigned long count)
{
        volatile u16 *p;
        u8 *buf = dst;

        if (PXSEG(port)) {
                while (count--)
                        *buf++ = *(volatile u8 *)port;
	} else if (CHECK_SH7751_PCIIO(port)) {
                volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);

                while (count--)
                        *buf++ = *bp;
	} else {
                p = (volatile u16 *)port2adr(port);
                while (count--)
                        *buf++ = *p & 0xff;
	}
}

void landisk_insw(unsigned long port, void *dst, unsigned long count)
{
        volatile u16 *p;
        u16 *buf = dst;

	if (PXSEG(port))
		p = (volatile u16 *)port;
	else if (CHECK_SH7751_PCIIO(port))
		p = (volatile u16 *)PCI_IOMAP(port);
	else
		p = (volatile u16 *)port2adr(port);
	while (count--)
		*buf++ = *p;
}

void landisk_insl(unsigned long port, void *dst, unsigned long count)
{
        u32 *buf = dst;

	if (CHECK_SH7751_PCIIO(port)) {
                volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);

                while (count--)
                        *buf++ = *p;
	} else
		maybebadio(port);
}

void landisk_outsb(unsigned long port, const void *src, unsigned long count)
{
        volatile u16 *p;
        const u8 *buf = src;

	if (PXSEG(port))
                while (count--)
                        ctrl_outb(*buf++, port);
	else if (CHECK_SH7751_PCIIO(port)) {
                volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port);

                while (count--)
                        *bp = *buf++;
	} else {
                p = (volatile u16 *)port2adr(port);
                while (count--)
                        *p = *buf++;
	}
}

void landisk_outsw(unsigned long port, const void *src, unsigned long count)
{
        volatile u16 *p;
        const u16 *buf = src;

	if (PXSEG(port))
                p = (volatile u16 *)port;
	else if (CHECK_SH7751_PCIIO(port))
                p = (volatile u16 *)PCI_IOMAP(port);
	else
                p = (volatile u16 *)port2adr(port);

        while (count--)
                *p = *buf++;
}

void landisk_outsl(unsigned long port, const void *src, unsigned long count)
{
        const u32 *buf = src;

	if (CHECK_SH7751_PCIIO(port)) {
                volatile u32 *p = (volatile u32 *)PCI_IOMAP(port);

                while (count--)
                        *p = *buf++;
	} else
		maybebadio(port);
}

void __iomem *landisk_ioport_map(unsigned long port, unsigned int size)
{
        if (PXSEG(port))
                return (void __iomem *)port;
        else if (CHECK_SH7751_PCIIO(port))
                return (void __iomem *)PCI_IOMAP(port);

        return (void __iomem *)port2adr(port);
}