summaryrefslogtreecommitdiffstats
path: root/arch/sh/kernel/io_generic.c
blob: f1b214d3bce3a578d36364cec856d254bb7badc5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
/*
 * arch/sh/kernel/io_generic.c
 *
 * Copyright (C) 2000  Niibe Yutaka
 * Copyright (C) 2005 - 2007 Paul Mundt
 *
 * Generic I/O routine. These can be used where a machine specific version
 * is not required.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/module.h>
#include <linux/io.h>
#include <asm/machvec.h>

#ifdef CONFIG_CPU_SH3
/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
 * workaround. */
/* I'm not sure SH7709 has this kind of bug */
#define dummy_read()	ctrl_inb(0xba000000)
#else
#define dummy_read()
#endif

unsigned long generic_io_base;

static inline void delay(void)
{
	ctrl_inw(0xa0000000);
}

u8 generic_inb(unsigned long port)
{
	return ctrl_inb((unsigned long __force)__ioport_map(port, 1));
}

u16 generic_inw(unsigned long port)
{
	return ctrl_inw((unsigned long __force)__ioport_map(port, 2));
}

u32 generic_inl(unsigned long port)
{
	return ctrl_inl((unsigned long __force)__ioport_map(port, 4));
}

u8 generic_inb_p(unsigned long port)
{
	unsigned long v = generic_inb(port);

	delay();
	return v;
}

u16 generic_inw_p(unsigned long port)
{
	unsigned long v = generic_inw(port);

	delay();
	return v;
}

u32 generic_inl_p(unsigned long port)
{
	unsigned long v = generic_inl(port);

	delay();
	return v;
}

/*
 * insb/w/l all read a series of bytes/words/longs from a fixed port
 * address. However as the port address doesn't change we only need to
 * convert the port address to real address once.
 */

void generic_insb(unsigned long port, void *dst, unsigned long count)
{
	volatile u8 *port_addr;
	u8 *buf = dst;

	port_addr = (volatile u8 __force *)__ioport_map(port, 1);
	while (count--)
		*buf++ = *port_addr;
}

void generic_insw(unsigned long port, void *dst, unsigned long count)
{
	volatile u16 *port_addr;
	u16 *buf = dst;

	port_addr = (volatile u16 __force *)__ioport_map(port, 2);
	while (count--)
		*buf++ = *port_addr;

	dummy_read();
}

void generic_insl(unsigned long port, void *dst, unsigned long count)
{
	volatile u32 *port_addr;
	u32 *buf = dst;

	port_addr = (volatile u32 __force *)__ioport_map(port, 4);
	while (count--)
		*buf++ = *port_addr;

	dummy_read();
}

void generic_outb(u8 b, unsigned long port)
{
	ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1));
}

void generic_outw(u16 b, unsigned long port)
{
	ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2));
}

void generic_outl(u32 b, unsigned long port)
{
	ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4));
}

void generic_outb_p(u8 b, unsigned long port)
{
	generic_outb(b, port);
	delay();
}

void generic_outw_p(u16 b, unsigned long port)
{
	generic_outw(b, port);
	delay();
}

void generic_outl_p(u32 b, unsigned long port)
{
	generic_outl(b, port);
	delay();
}

/*
 * outsb/w/l all write a series of bytes/words/longs to a fixed port
 * address. However as the port address doesn't change we only need to
 * convert the port address to real address once.
 */
void generic_outsb(unsigned long port, const void *src, unsigned long count)
{
	volatile u8 *port_addr;
	const u8 *buf = src;

	port_addr = (volatile u8 __force *)__ioport_map(port, 1);

	while (count--)
		*port_addr = *buf++;
}

void generic_outsw(unsigned long port, const void *src, unsigned long count)
{
	volatile u16 *port_addr;
	const u16 *buf = src;

	port_addr = (volatile u16 __force *)__ioport_map(port, 2);

	while (count--)
		*port_addr = *buf++;

	dummy_read();
}

void generic_outsl(unsigned long port, const void *src, unsigned long count)
{
	volatile u32 *port_addr;
	const u32 *buf = src;

	port_addr = (volatile u32 __force *)__ioport_map(port, 4);
	while (count--)
		*port_addr = *buf++;

	dummy_read();
}

u8 generic_readb(void __iomem *addr)
{
	return ctrl_inb((unsigned long __force)addr);
}

u16 generic_readw(void __iomem *addr)
{
	return ctrl_inw((unsigned long __force)addr);
}

u32 generic_readl(void __iomem *addr)
{
	return ctrl_inl((unsigned long __force)addr);
}

void generic_writeb(u8 b, void __iomem *addr)
{
	ctrl_outb(b, (unsigned long __force)addr);
}

void generic_writew(u16 b, void __iomem *addr)
{
	ctrl_outw(b, (unsigned long __force)addr);
}

void generic_writel(u32 b, void __iomem *addr)
{
	ctrl_outl(b, (unsigned long __force)addr);
}

void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
{
	return (void __iomem *)(addr + generic_io_base);
}

void generic_ioport_unmap(void __iomem *addr)
{
}