summaryrefslogtreecommitdiffstats
path: root/drivers/mtd/nand/w90p910_nand.c
blob: 7680e731348a5b7342a0b9c8c50193f4bf31af1d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
/*
 * Copyright (c) 2009 Nuvoton technology corporation.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation;version 2 of the License.
 *
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>

#define REG_FMICSR   	0x00
#define REG_SMCSR    	0xa0
#define REG_SMISR    	0xac
#define REG_SMCMD    	0xb0
#define REG_SMADDR   	0xb4
#define REG_SMDATA   	0xb8

#define RESET_FMI	0x01
#define NAND_EN		0x08
#define READYBUSY	(0x01 << 18)

#define SWRST		0x01
#define PSIZE		(0x01 << 3)
#define DMARWEN		(0x03 << 1)
#define BUSWID		(0x01 << 4)
#define ECC4EN		(0x01 << 5)
#define WP		(0x01 << 24)
#define NANDCS		(0x01 << 25)
#define ENDADDR		(0x01 << 31)

#define read_data_reg(dev)		\
	__raw_readl((dev)->reg + REG_SMDATA)

#define write_data_reg(dev, val)	\
	__raw_writel((val), (dev)->reg + REG_SMDATA)

#define write_cmd_reg(dev, val)		\
	__raw_writel((val), (dev)->reg + REG_SMCMD)

#define write_addr_reg(dev, val)	\
	__raw_writel((val), (dev)->reg + REG_SMADDR)

struct w90p910_nand {
	struct mtd_info mtd;
	struct nand_chip chip;
	void __iomem *reg;
	struct clk *clk;
	spinlock_t lock;
};

static const struct mtd_partition partitions[] = {
	{
	 .name = "NAND FS 0",
	 .offset = 0,
	 .size = 8 * 1024 * 1024
	},
	{
	 .name = "NAND FS 1",
	 .offset = MTDPART_OFS_APPEND,
	 .size = MTDPART_SIZ_FULL
	}
};

static unsigned char w90p910_nand_read_byte(struct mtd_info *mtd)
{
	unsigned char ret;
	struct w90p910_nand *nand;

	nand = container_of(mtd, struct w90p910_nand, mtd);

	ret = (unsigned char)read_data_reg(nand);

	return ret;
}

static void w90p910_nand_read_buf(struct mtd_info *mtd,
						unsigned char *buf, int len)
{
	int i;
	struct w90p910_nand *nand;

	nand = container_of(mtd, struct w90p910_nand, mtd);

	for (i = 0; i < len; i++)
		buf[i] = (unsigned char)read_data_reg(nand);
}

static void w90p910_nand_write_buf(struct mtd_info *mtd,
					const unsigned char *buf, int len)
{
	int i;
	struct w90p910_nand *nand;

	nand = container_of(mtd, struct w90p910_nand, mtd);

	for (i = 0; i < len; i++)
		write_data_reg(nand, buf[i]);
}

static int w90p910_verify_buf(struct mtd_info *mtd,
					const unsigned char *buf, int len)
{
	int i;
	struct w90p910_nand *nand;

	nand = container_of(mtd, struct w90p910_nand, mtd);

	for (i = 0; i < len; i++) {
		if (buf[i] != (unsigned char)read_data_reg(nand))
			return -EFAULT;
	}

	return 0;
}

static int w90p910_check_rb(struct w90p910_nand *nand)
{
	unsigned int val;
	spin_lock(&nand->lock);
	val = __raw_readl(REG_SMISR);
	val &= READYBUSY;
	spin_unlock(&nand->lock);

	return val;
}

static int w90p910_nand_devready(struct mtd_info *mtd)
{
	struct w90p910_nand *nand;
	int ready;

	nand = container_of(mtd, struct w90p910_nand, mtd);

	ready = (w90p910_check_rb(nand)) ? 1 : 0;
	return ready;
}

static void w90p910_nand_command_lp(struct mtd_info *mtd,
			unsigned int command, int column, int page_addr)
{
	register struct nand_chip *chip = mtd->priv;
	struct w90p910_nand *nand;

	nand = container_of(mtd, struct w90p910_nand, mtd);

	if (command == NAND_CMD_READOOB) {
		column += mtd->writesize;
		command = NAND_CMD_READ0;
	}

	write_cmd_reg(nand, command & 0xff);

	if (column != -1 || page_addr != -1) {

		if (column != -1) {
			if (chip->options & NAND_BUSWIDTH_16)
				column >>= 1;
			write_addr_reg(nand, column);
			write_addr_reg(nand, column >> 8 | ENDADDR);
		}
		if (page_addr != -1) {
			write_addr_reg(nand, page_addr);

			if (chip->chipsize > (128 << 20)) {
				write_addr_reg(nand, page_addr >> 8);
				write_addr_reg(nand, page_addr >> 16 | ENDADDR);
			} else {
				write_addr_reg(nand, page_addr >> 8 | ENDADDR);
			}
		}
	}

	switch (command) {
	case NAND_CMD_CACHEDPROG:
	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_SEQIN:
	case NAND_CMD_RNDIN:
	case NAND_CMD_STATUS:
	case NAND_CMD_DEPLETE1:
		return;

	case NAND_CMD_STATUS_ERROR:
	case NAND_CMD_STATUS_ERROR0:
	case NAND_CMD_STATUS_ERROR1:
	case NAND_CMD_STATUS_ERROR2:
	case NAND_CMD_STATUS_ERROR3:
		udelay(chip->chip_delay);
		return;

	case NAND_CMD_RESET:
		if (chip->dev_ready)
			break;
		udelay(chip->chip_delay);

		write_cmd_reg(nand, NAND_CMD_STATUS);
		write_cmd_reg(nand, command);

		while (!w90p910_check_rb(nand))
			;

		return;

	case NAND_CMD_RNDOUT:
		write_cmd_reg(nand, NAND_CMD_RNDOUTSTART);
		return;

	case NAND_CMD_READ0:

		write_cmd_reg(nand, NAND_CMD_READSTART);
	default:

		if (!chip->dev_ready) {
			udelay(chip->chip_delay);
			return;
		}
	}

	/* Apply this short delay always to ensure that we do wait tWB in
	 * any case on any machine. */
	ndelay(100);

	while (!chip->dev_ready(mtd))
		;
}


static void w90p910_nand_enable(struct w90p910_nand *nand)
{
	unsigned int val;
	spin_lock(&nand->lock);
	__raw_writel(RESET_FMI, (nand->reg + REG_FMICSR));

	val = __raw_readl(nand->reg + REG_FMICSR);

	if (!(val & NAND_EN))
		__raw_writel(val | NAND_EN, REG_FMICSR);

	val = __raw_readl(nand->reg + REG_SMCSR);

	val &= ~(SWRST|PSIZE|DMARWEN|BUSWID|ECC4EN|NANDCS);
	val |= WP;

	__raw_writel(val, nand->reg + REG_SMCSR);

	spin_unlock(&nand->lock);
}

static int __devinit w90p910_nand_probe(struct platform_device *pdev)
{
	struct w90p910_nand *w90p910_nand;
	struct nand_chip *chip;
	int retval;
	struct resource *res;

	retval = 0;

	w90p910_nand = kzalloc(sizeof(struct w90p910_nand), GFP_KERNEL);
	if (!w90p910_nand)
		return -ENOMEM;
	chip = &(w90p910_nand->chip);

	w90p910_nand->mtd.priv	= chip;
	w90p910_nand->mtd.owner	= THIS_MODULE;
	spin_lock_init(&w90p910_nand->lock);

	w90p910_nand->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(w90p910_nand->clk)) {
		retval = -ENOENT;
		goto fail1;
	}
	clk_enable(w90p910_nand->clk);

	chip->cmdfunc		= w90p910_nand_command_lp;
	chip->dev_ready		= w90p910_nand_devready;
	chip->read_byte		= w90p910_nand_read_byte;
	chip->write_buf		= w90p910_nand_write_buf;
	chip->read_buf		= w90p910_nand_read_buf;
	chip->verify_buf	= w90p910_verify_buf;
	chip->chip_delay	= 50;
	chip->options		= 0;
	chip->ecc.mode		= NAND_ECC_SOFT;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		retval = -ENXIO;
		goto fail1;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		retval = -EBUSY;
		goto fail1;
	}

	w90p910_nand->reg = ioremap(res->start, resource_size(res));
	if (!w90p910_nand->reg) {
		retval = -ENOMEM;
		goto fail2;
	}

	w90p910_nand_enable(w90p910_nand);

	if (nand_scan(&(w90p910_nand->mtd), 1)) {
		retval = -ENXIO;
		goto fail3;
	}

	add_mtd_partitions(&(w90p910_nand->mtd), partitions,
						ARRAY_SIZE(partitions));

	platform_set_drvdata(pdev, w90p910_nand);

	return retval;

fail3:	iounmap(w90p910_nand->reg);
fail2:	release_mem_region(res->start, resource_size(res));
fail1:	kfree(w90p910_nand);
	return retval;
}

static int __devexit w90p910_nand_remove(struct platform_device *pdev)
{
	struct w90p910_nand *w90p910_nand = platform_get_drvdata(pdev);
	struct resource *res;

	iounmap(w90p910_nand->reg);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, resource_size(res));

	clk_disable(w90p910_nand->clk);
	clk_put(w90p910_nand->clk);

	kfree(w90p910_nand);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver w90p910_nand_driver = {
	.probe		= w90p910_nand_probe,
	.remove		= __devexit_p(w90p910_nand_remove),
	.driver		= {
		.name	= "w90p910-fmi",
		.owner	= THIS_MODULE,
	},
};

static int __init w90p910_nand_init(void)
{
	return platform_driver_register(&w90p910_nand_driver);
}

static void __exit w90p910_nand_exit(void)
{
	platform_driver_unregister(&w90p910_nand_driver);
}

module_init(w90p910_nand_init);
module_exit(w90p910_nand_exit);

MODULE_AUTHOR("Wan ZongShun <mcuos.com@gmail.com>");
MODULE_DESCRIPTION("w90p910 nand driver!");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:w90p910-fmi");