summaryrefslogtreecommitdiffstats
path: root/drivers/video/geode/gxfb.h
blob: c21f9dc5e0c18206801fd2f69b788858714e99f9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
/*
 * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
 *
 * Geode GX2 register tables
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#ifndef _GXFB_H_
#define _GXFB_H_

#include <linux/io.h>

/* Display Controller registers (table 6-38 from the data book) */
enum dc_registers {
	DC_UNLOCK = 0,
	DC_GENERAL_CFG,
	DC_DISPLAY_CFG,
	DC_RSVD_0,

	DC_FB_ST_OFFSET,
	DC_CB_ST_OFFSET,
	DC_CURS_ST_OFFSET,
	DC_ICON_ST_OFFSET,

	DC_VID_Y_ST_OFFSET,
	DC_VID_U_ST_OFFSET,
	DC_VID_V_ST_OFFSET,
	DC_RSVD_1,

	DC_LINE_SIZE,
	DC_GFX_PITCH,
	DC_VID_YUV_PITCH,
	DC_RSVD_2,

	DC_H_ACTIVE_TIMING,
	DC_H_BLANK_TIMING,
	DC_H_SYNC_TIMING,
	DC_RSVD_3,

	DC_V_ACTIVE_TIMING,
	DC_V_BLANK_TIMING,
	DC_V_SYNC_TIMING,
	DC_RSVD_4,

	DC_CURSOR_X,
	DC_CURSOR_Y,
	DC_ICON_X,
	DC_LINE_CNT,

	DC_PAL_ADDRESS,
	DC_PAL_DATA,
	DC_DFIFO_DIAG,
	DC_CFIFO_DIAG,

	DC_VID_DS_DELTA,
	DC_GLIU0_MEM_OFFSET,
	DC_RSVD_5,
	DC_DV_ACC, /* 0x8c */
};

#define DC_UNLOCK_LOCK			0x00000000
#define DC_UNLOCK_UNLOCK		0x00004758	/* magic value */

#define DC_GENERAL_CFG_YUVM		(1 << 20)
#define DC_GENERAL_CFG_VDSE		(1 << 19)
#define DC_GENERAL_CFG_DFHPEL_SHIFT	12
#define DC_GENERAL_CFG_DFHPSL_SHIFT	8
#define DC_GENERAL_CFG_DECE		(1 << 6)
#define DC_GENERAL_CFG_CMPE		(1 << 5)
#define DC_GENERAL_CFG_VIDE		(1 << 3)
#define DC_GENERAL_CFG_ICNE		(1 << 2)
#define DC_GENERAL_CFG_CURE		(1 << 1)
#define DC_GENERAL_CFG_DFLE		(1 << 0)

#define DC_DISPLAY_CFG_A20M		(1 << 31)
#define DC_DISPLAY_CFG_A18M		(1 << 30)
#define DC_DISPLAY_CFG_PALB		(1 << 25)
#define DC_DISPLAY_CFG_DISP_MODE_24BPP	(1 << 9)
#define DC_DISPLAY_CFG_DISP_MODE_16BPP	(1 << 8)
#define DC_DISPLAY_CFG_DISP_MODE_8BPP	(0)
#define DC_DISPLAY_CFG_VDEN		(1 << 4)
#define DC_DISPLAY_CFG_GDEN		(1 << 3)
#define DC_DISPLAY_CFG_TGEN		(1 << 0)


/*
 * Video Processor registers (table 6-54).
 * There is space for 64 bit values, but we never use more than the
 * lower 32 bits.  The actual register save/restore code only bothers
 * to restore those 32 bits.
 */
enum vp_registers {
	VP_VCFG = 0,
	VP_DCFG,

	VP_VX,
	VP_VY,

	VP_VS,
	VP_VCK,

	VP_VCM,
	VP_GAR,

	VP_GDR,
	VP_RSVD_0,

	VP_MISC,
	VP_CCS,

	VP_RSVD_1,
	VP_RSVD_2,

	VP_RSVD_3,
	VP_VDC,

	VP_VCO,
	VP_CRC,

	VP_CRC32,
	VP_VDE,

	VP_CCK,
	VP_CCM,

	VP_CC1,
	VP_CC2,

	VP_A1X,
	VP_A1Y,

	VP_A1C,
	VP_A1T,

	VP_A2X,
	VP_A2Y,

	VP_A2C,
	VP_A2T,

	VP_A3X,
	VP_A3Y,

	VP_A3C,
	VP_A3T,

	VP_VRR,
	VP_AWT,

	VP_VTM, /* 0x130 */
};

#define VP_VCFG_VID_EN			(1 << 0)

#define VP_DCFG_DAC_VREF		(1 << 26)
#define VP_DCFG_GV_GAM			(1 << 21)
#define VP_DCFG_VG_CK			(1 << 20)
#define VP_DCFG_CRT_SYNC_SKW_DEFAULT	(1 << 16)
#define VP_DCFG_CRT_SYNC_SKW		((1 << 14) | (1 << 15) | (1 << 16))
#define VP_DCFG_CRT_VSYNC_POL		(1 << 9)
#define VP_DCFG_CRT_HSYNC_POL		(1 << 8)
#define VP_DCFG_FP_DATA_EN		(1 << 7)	/* undocumented */
#define VP_DCFG_FP_PWR_EN		(1 << 6)	/* undocumented */
#define VP_DCFG_DAC_BL_EN		(1 << 3)
#define VP_DCFG_VSYNC_EN		(1 << 2)
#define VP_DCFG_HSYNC_EN		(1 << 1)
#define VP_DCFG_CRT_EN			(1 << 0)

#define VP_MISC_GAM_EN			(1 << 0)
#define VP_MISC_DACPWRDN		(1 << 10)
#define VP_MISC_APWRDN			(1 << 11)


/*
 * Flat Panel registers (table 6-55).
 * Also 64 bit registers; see above note about 32-bit handling.
 */

/* we're actually in the VP register space, starting at address 0x400 */
#define VP_FP_START		0x400

enum fp_registers {
	FP_PT1 = 0,
	FP_PT2,

	FP_PM,
	FP_DFC,

	FP_BLFSR,
	FP_RLFSR,

	FP_FMI,
	FP_FMD,

	FP_RSVD_0,
	FP_DCA,

	FP_DMD,
	FP_CRC,

	FP_FBB, /* 0x460 */
};

#define FP_PT1_VSIZE_SHIFT		16		/* undocumented? */
#define FP_PT1_VSIZE_MASK		0x7FF0000	/* undocumented? */

#define FP_PT2_HSP			(1 << 22)
#define FP_PT2_VSP			(1 << 23)

#define FP_PM_P				(1 << 24)       /* panel power on */
#define FP_PM_PANEL_PWR_UP		(1 << 3)        /* r/o */
#define FP_PM_PANEL_PWR_DOWN		(1 << 2)        /* r/o */
#define FP_PM_PANEL_OFF			(1 << 1)        /* r/o */
#define FP_PM_PANEL_ON			(1 << 0)        /* r/o */

#define FP_DFC_NFI			((1 << 4) | (1 << 5) | (1 << 6))


/* register access functions */

static inline uint32_t read_dc(struct geodefb_par *par, int reg)
{
	return readl(par->dc_regs + 4*reg);
}

static inline void write_dc(struct geodefb_par *par, int reg, uint32_t val)
{
	writel(val, par->dc_regs + 4*reg);
}


static inline uint32_t read_vp(struct geodefb_par *par, int reg)
{
	return readl(par->vid_regs + 8*reg);
}

static inline void write_vp(struct geodefb_par *par, int reg, uint32_t val)
{
	writel(val, par->vid_regs + 8*reg);
}

static inline uint32_t read_fp(struct geodefb_par *par, int reg)
{
	return readl(par->vid_regs + 8*reg + VP_FP_START);
}

static inline void write_fp(struct geodefb_par *par, int reg, uint32_t val)
{
	writel(val, par->vid_regs + 8*reg + VP_FP_START);
}


/* MSRs are defined in asm/geode.h; their bitfields are here */

#define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3	(1 << 3)
#define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2	(1 << 2)
#define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2	(1 << 1)

#define MSR_GLCP_DOTPLL_LOCK		(1 << 25)	/* r/o */
#define MSR_GLCP_DOTPLL_BYPASS		(1 << 15)
#define MSR_GLCP_DOTPLL_DOTRESET	(1 << 0)

#define MSR_GX_MSR_PADSEL_MASK		0x3FFFFFFF	/* undocumented? */
#define MSR_GX_MSR_PADSEL_TFT		0x1FFFFFFF	/* undocumented? */

#define MSR_GX_GLD_MSR_CONFIG_FP	(1 << 3)

#endif