1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
|
#ifndef __LINUX_SERIAL_SCI_H
#define __LINUX_SERIAL_SCI_H
#include <linux/serial_core.h>
#include <linux/sh_dma.h>
/*
* Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
*/
#define SCIx_NOT_SUPPORTED (-1)
enum {
SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
SCBRR_ALGO_1, /* clk / (16 * bps) */
SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
SCBRR_ALGO_3, /* clk / (8 * bps) */
SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
};
#define SCSCR_TIE (1 << 7)
#define SCSCR_RIE (1 << 6)
#define SCSCR_TE (1 << 5)
#define SCSCR_RE (1 << 4)
#define SCSCR_REIE (1 << 3) /* not supported by all parts */
#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
#define SCSCR_CKE1 (1 << 1)
#define SCSCR_CKE0 (1 << 0)
/* SCxSR SCI */
#define SCI_TDRE 0x80
#define SCI_RDRF 0x40
#define SCI_ORER 0x20
#define SCI_FER 0x10
#define SCI_PER 0x08
#define SCI_TEND 0x04
#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
/* SCxSR SCIF, HSCIF */
#define SCIF_ER 0x0080
#define SCIF_TEND 0x0040
#define SCIF_TDFE 0x0020
#define SCIF_BRK 0x0010
#define SCIF_FER 0x0008
#define SCIF_PER 0x0004
#define SCIF_RDF 0x0002
#define SCIF_DR 0x0001
#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
/* SCSPTR, optional */
#define SCSPTR_RTSIO (1 << 7)
#define SCSPTR_CTSIO (1 << 5)
#define SCSPTR_SPB2IO (1 << 1)
#define SCSPTR_SPB2DT (1 << 0)
/* HSSRR HSCIF */
#define HSCIF_SRE 0x8000
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
SCIx_RXI_IRQ,
SCIx_TXI_IRQ,
SCIx_BRI_IRQ,
SCIx_NR_IRQS,
SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
};
enum {
SCIx_PROBE_REGTYPE,
SCIx_SCI_REGTYPE,
SCIx_IRDA_REGTYPE,
SCIx_SCIFA_REGTYPE,
SCIx_SCIFB_REGTYPE,
SCIx_SH2_SCIF_FIFODATA_REGTYPE,
SCIx_SH3_SCIF_REGTYPE,
SCIx_SH4_SCIF_REGTYPE,
SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
SCIx_SH4_SCIF_FIFODATA_REGTYPE,
SCIx_SH7705_SCIF_REGTYPE,
SCIx_HSCIF_REGTYPE,
SCIx_NR_REGTYPES,
};
#define SCIx_IRQ_MUXED(irq) \
{ \
[SCIx_ERI_IRQ] = (irq), \
[SCIx_RXI_IRQ] = (irq), \
[SCIx_TXI_IRQ] = (irq), \
[SCIx_BRI_IRQ] = (irq), \
}
#define SCIx_IRQ_IS_MUXED(port) \
((port)->irqs[SCIx_ERI_IRQ] == \
(port)->irqs[SCIx_RXI_IRQ]) || \
((port)->irqs[SCIx_ERI_IRQ] && \
((port)->irqs[SCIx_RXI_IRQ] < 0))
/*
* SCI register subset common for all port types.
* Not all registers will exist on all parts.
*/
enum {
SCSMR, SCBRR, SCSCR, SCxSR,
SCFCR, SCFDR, SCxTDR, SCxRDR,
SCLSR, SCTFDR, SCRFDR, SCSPTR,
HSSRR,
SCIx_NR_REGS,
};
struct device;
struct plat_sci_port_ops {
void (*init_pins)(struct uart_port *, unsigned int cflag);
};
/*
* Port-specific capabilities
*/
#define SCIx_HAVE_RTSCTS (1 << 0)
/*
* Platform device specific platform_data struct
*/
struct plat_sci_port {
unsigned long mapbase; /* resource base */
unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
upf_t flags; /* UPF_* flags */
unsigned long capabilities; /* Port features/capabilities */
unsigned int sampling_rate;
unsigned int scbrr_algo_id; /* SCBRR calculation algo */
unsigned int scscr; /* SCSCR initialization */
/*
* Platform overrides if necessary, defaults otherwise.
*/
int port_reg;
unsigned char regshift;
unsigned char regtype;
struct plat_sci_port_ops *ops;
unsigned int dma_slave_tx;
unsigned int dma_slave_rx;
};
#endif /* __LINUX_SERIAL_SCI_H */
|
