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authorWill Deacon <will.deacon@arm.com>2011-08-09 12:24:07 +0100
committerWill Deacon <will.deacon@arm.com>2011-10-17 10:01:11 +0100
commit4a139b64703115e41e1a4e16ebf7eb93d0a0e349 (patch)
tree88a5c30d4946dcd5309488ce3f3b0e0805180470
parent28763487b19eacca70374c1f62b3b8da2bba464f (diff)
ARM: versatile: convert logical CPU numbers to physical numbers
This patch uses the new cpu_logical_map() macro for converting logical CPU numbers into physical numbers when dealing with the pen_release variable in the SMP boot and CPU hotplug paths. Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm/mach-realview/hotplug.c2
-rw-r--r--arch/arm/mach-vexpress/hotplug.c2
-rw-r--r--arch/arm/plat-versatile/platsmp.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index a87523d095e..ac1aed2a8da 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -69,7 +69,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
:
: "memory", "cc");
- if (pen_release == cpu) {
+ if (pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index ea4cbfb90a6..2866ed8c4b0 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -70,7 +70,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
:
: "memory", "cc");
- if (pen_release == cpu) {
+ if (pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 51ecfea09b2..92f18d372b6 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -77,7 +77,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* since we haven't sent them a soft interrupt, they shouldn't
* be there.
*/
- write_pen_release(cpu);
+ write_pen_release(cpu_logical_map(cpu));
/*
* Send the secondary CPU a soft interrupt, thereby causing