diff options
| author | Gavin Shan <shangw@linux.vnet.ibm.com> | 2012-09-11 16:59:46 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-09-11 16:59:46 -0600 |
| commit | 4c2245bb5c9c6e9950ee8919b4462dfa77f7a28f (patch) | |
| tree | 40294aad43963b4e4e3ccd6d008aab9628465c7b | |
| parent | c121504e899c19f7e25b4894f616475073876361 (diff) | |
powerpc/PCI: Override pcibios_window_alignment()
This patch implements pcibios_window_alignment() so powerpc platforms can
force P2P bridge windows to be at larger alignments than the PCI spec
requires.
[bhelgaas: changelog]
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| -rw-r--r-- | arch/powerpc/include/asm/machdep.h | 3 | ||||
| -rw-r--r-- | arch/powerpc/kernel/pci-common.c | 20 |
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index 42ce570812c..f7706d722b3 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -214,6 +214,9 @@ struct machdep_calls { /* Called after scan and before resource survey */ void (*pcibios_fixup_phb)(struct pci_controller *hose); + /* Called during PCI resource reassignment */ + resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type); + /* Called to shutdown machine specific hardware not already controlled * by other drivers. */ diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 2aa04f29e1d..43fea543d68 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -99,6 +99,26 @@ void pcibios_free_controller(struct pci_controller *phb) kfree(phb); } +/* + * The function is used to return the minimal alignment + * for memory or I/O windows of the associated P2P bridge. + * By default, 4KiB alignment for I/O windows and 1MiB for + * memory windows. + */ +resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type) +{ + if (ppc_md.pcibios_window_alignment) + return ppc_md.pcibios_window_alignment(bus, type); + + /* + * PCI core will figure out the default + * alignment: 4KiB for I/O and 1MiB for + * memory window. + */ + return 1; +} + static resource_size_t pcibios_io_size(const struct pci_controller *hose) { #ifdef CONFIG_PPC64 |