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authorDmitry Artamonow <mad_soft@inbox.ru>2012-03-06 12:45:43 +0400
committerOlof Johansson <olof@lixom.net>2012-03-07 14:39:55 -0800
commit795d5fd4b8b06944976c95e8592e17e2d415aa81 (patch)
tree70703693cb917fbe780303f10d813d0cfcf2649b
parent448b98047c61dd612fc3a41a2b9479da77ace27d (diff)
arm/tegra: add timeout to PCIe PLL lock detection loop
Tegra PCIe driver waits for PLL to lock using busy loop. If PLL fails to lock for some reason, this leads to silent lockup while booting (as PCIe code is not modular). Fix by adding timeout, so if PLL doesn't lock in a couple of seconds, just PCIe driver fails and machine continues to boot. Signed-off-by: Dmitry Artamonow <mad_soft@inbox.ru> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Olof Johansson <olof@lixom.net>
-rw-r--r--arch/arm/mach-tegra/pcie.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index af8b6343572..0a1dec69439 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
afi_writel(0, AFI_MSI_BAR_SZ);
}
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
{
u32 val, reg;
- int i;
+ int i, timeout;
/* Enable slot clock and pulse the reset signals */
for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
pads_writel(0xfa5cfa5c, 0xc8);
/* Wait for the PLL to lock */
+ timeout = 2000;
do {
val = pads_readl(PADS_PLL_CTL);
+ mdelay(1);
+ if (--timeout == 0) {
+ pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+ return -EBUSY;
+ }
} while (!(val & PADS_PLL_CTL_LOCKDET));
/* turn off IDDQ override */
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
if (err)
return err;
- tegra_pcie_enable_controller();
+ err = tegra_pcie_enable_controller();
+ if (err)
+ return err;
/* setup the AFI address translations */
tegra_pcie_setup_translations();