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authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2013-04-18 18:35:59 +0100
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2013-05-23 10:45:14 +0100
commiteeb25fd5913961562f1f4197b5485cafa54f4fe1 (patch)
tree1b6eba325eace025b637d853a58294fc6765bda5
parent73158b77c97bebdf10533a31044c45e078b43507 (diff)
ARM: dts: omap: cpus/cpu nodes dts updates
This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-rw-r--r--arch/arm/boot/dts/omap2.dtsi6
-rw-r--r--arch/arm/boot/dts/omap3.dtsi5
-rw-r--r--arch/arm/boot/dts/omap4.dtsi7
-rw-r--r--arch/arm/boot/dts/omap5.dtsi7
4 files changed, 24 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa7487d4d..4aac404608c 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -21,8 +21,12 @@
};
cpus {
- cpu@0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ cpu {
compatible = "arm,arm1136jf-s";
+ device_type = "cpu";
};
};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 82a404da1c0..ba05d7fc59f 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -21,8 +21,13 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0x0>;
};
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a5642882c8..33a94509a29 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -28,13 +28,20 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
next-level-cache = <&L2>;
+ reg = <0x0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
+ device_type = "cpu";
next-level-cache = <&L2>;
+ reg = <0x1>;
};
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff82582..35a6536a10b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -34,11 +34,18 @@
};
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
+ reg = <0x0>;
};
cpu@1 {
+ device_type = "cpu";
compatible = "arm,cortex-a15";
+ reg = <0x1>;
};
};