diff options
| author | Michael Hench <michaelhench@gmail.com> | 2011-07-26 15:07:42 -0500 |
|---|---|---|
| committer | Artem Bityutskiy <artem.bityutskiy@intel.com> | 2011-09-11 15:02:17 +0300 |
| commit | f975c6bcb07caacff7fa9904e5d2daa51bcf549d (patch) | |
| tree | 49dd07b49b14815d382ba3a578d88b167defb6b4 | |
| parent | 4aa10626adbc27dcf2e3462bb82b4963c5545669 (diff) | |
mtd: eLBC NAND: update ecc_stats.corrected when lteccr available
Signed-off-by: Michael Hench <MichaelHench@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@intel.com>
| -rw-r--r-- | drivers/mtd/nand/fsl_elbc_nand.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index acc27ee0474..eedd8ee2c9a 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -243,6 +243,25 @@ static int fsl_elbc_run_command(struct mtd_info *mtd) return -EIO; } + if (chip->ecc.mode != NAND_ECC_HW) + return 0; + + if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { + uint32_t lteccr = in_be32(&lbc->lteccr); + /* + * if command was a full page read and the ELBC + * has the LTECCR register, then bits 12-15 (ppc order) of + * LTECCR indicates which 512 byte sub-pages had fixed errors. + * bits 28-31 are uncorrectable errors, marked elsewhere. + * for small page nand only 1 bit is used. + * if the ELBC doesn't have the lteccr register it reads 0 + */ + if (lteccr & 0x000F000F) + out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ + if (lteccr & 0x000F0000) + mtd->ecc_stats.corrected++; + } + return 0; } |