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authorRoger Quadros <rogerq@ti.com>2014-11-14 17:37:39 +0200
committerMarc Kleine-Budde <mkl@pengutronix.de>2014-11-17 12:19:27 +0100
commit3ff9027ca6b00e194d2eae353febf7233cfcc1ea (patch)
tree57a9c2af5f00837a2b4d22fa661e1ac6791e045b /CREDITS
parentbbf914300509f038c807360d755bd606785be6c9 (diff)
can: c_can: Add syscon/regmap RAMINIT mechanism
Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver. To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM. Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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