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authorH. Peter Anvin <hpa@linux.intel.com>2014-01-29 09:07:00 -0800
committerH. Peter Anvin <hpa@linux.intel.com>2014-01-29 09:07:00 -0800
commit4064e0ea3c0e9427e6c22392c4b69b4bfa1b7125 (patch)
tree888b52771f540552a9dc85521d8dddf66eba9aeb /Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
parent9b3965f7401b0cc3ed2c228085a4c13b1c9243b1 (diff)
parentf4bcd8ccddb02833340652e9f46f5127828eb79d (diff)
Merge commit 'f4bcd8ccddb02833340652e9f46f5127828eb79d' into x86/build
Bring in upstream merge of x86/kaslr for future patches. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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+Allwinner SoCs High Speed Timer Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sun5i-a13-hstimer" or
+ "allwinner,sun7i-a20-hstimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
+ one)
+- clocks: phandle to the source clock (usually the AHB clock)
+
+Example:
+
+timer@01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 1>,
+ <0 52 1>,
+ <0 53 1>,
+ <0 54 1>;
+ clocks = <&ahb1_gates 19>;
+};