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authorWill Deacon <will.deacon@arm.com>2013-02-01 10:28:36 +0000
committerWill Deacon <will.deacon@arm.com>2013-02-01 10:28:36 +0000
commit9e02e394c7d7fdc2570a73fb7fc6da3c79f6db2a (patch)
tree225262f25e7b6518b47fbf68b1311cee61e3ad83 /Documentation
parent5b91ab0abc957145c3ff6be03eb9a3901797019f (diff)
parent8266891e252f35dcb189c3f2371cfa588f8a8818 (diff)
Merge branch 'for-will/arch-timer-unification' of git://linux-arm.org/linux-mr into for-arm-soc/arch-timers
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/arch_timer.txt7
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index 52478c83d0c..20746e5abe6 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -1,13 +1,14 @@
* ARM architected timer
-ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
-provides per-cpu timers.
+ARM cores may have a per-core architected timer, which provides per-cpu timers.
The timer is attached to a GIC to deliver its per-processor interrupts.
** Timer node properties:
-- compatible : Should at least contain "arm,armv7-timer".
+- compatible : Should at least contain one of
+ "arm,armv7-timer"
+ "arm,armv8-timer"
- interrupts : Interrupt list for secure, non-secure, virtual and
hypervisor timers, in that order.