ARM: LPC32xx: DTS files for device tree conversion

This patch adds the dts files for the reference machine of LPC32xx:

* arch/arm/boot/dts/lpc32xx.dtsi: Include for devices based on LPC32xx
* arch/arm/boot/dts/phy3250.dts: Board support for PHYTEC phyCORE-LPC3250

Signed-off-by: Roland Stigge <stigge@antcom.de>

1 files changed, 145 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
new file mode 100644
index 00000000000..0167e86314c
--- /dev/null
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -0,0 +1,145 @@
+/*
+ * PHYTEC phyCORE-LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "lpc32xx.dtsi"
+
+/ {
+	model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
+	compatible = "phytec,phy3250", "nxp,lpc3250";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x4000000>;
+	};
+
+	ahb {
+		mac: ethernet@31060000 {
+			phy-mode = "rmii";
+			use-iram;
+		};
+
+		/* Here, choose exactly one from: ohci, usbd */
+		ohci@31020000 {
+			transceiver = <&isp1301>;
+			status = "okay";
+		};
+
+/*
+		usbd@31020000 {
+			transceiver = <&isp1301>;
+			status = "okay";
+		};
+*/
+
+		clcd@31040000 {
+			status = "okay";
+		};
+
+		/* 64MB Flash via SLC NAND controller */
+		slc: flash@20020000 {
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mtd0@00000000 {
+				label = "phy3250-boot";
+				reg = <0x00000000 0x00064000>;
+				read-only;
+			};
+
+			mtd1@00064000 {
+				label = "phy3250-uboot";
+				reg = <0x00064000 0x00190000>;
+				read-only;
+			};
+
+			mtd2@001f4000 {
+				label = "phy3250-ubt-prms";
+				reg = <0x001f4000 0x00010000>;
+			};
+
+			mtd3@00204000 {
+				label = "phy3250-kernel";
+				reg = <0x00204000 0x00400000>;
+			};
+
+			mtd4@00604000 {
+				label = "phy3250-rootfs";
+				reg = <0x00604000 0x039fc000>;
+			};
+		};
+
+		apb {
+			i2c1: i2c@400A0000 {
+				clock-frequency = <100000>;
+
+				pcf8563: rtc@51 {
+					compatible = "nxp,pcf8563";
+					reg = <0x51>;
+				};
+
+				uda1380: uda1380@18 {
+					compatible = "nxp,uda1380";
+					reg = <0x18>;
+					power-gpio = <&gpio 0x59 0>;
+					reset-gpio = <&gpio 0x51 0>;
+					dac-clk = "wspll";
+				};
+			};
+
+			i2c2: i2c@400A8000 {
+				clock-frequency = <100000>;
+			};
+
+			i2cusb: i2c@31020300 {
+				clock-frequency = <100000>;
+
+				isp1301: usb-transceiver@2c {
+					compatible = "nxp,isp1301";
+					reg = <0x2c>;
+				};
+			};
+
+			ssp0: ssp@20084000 {
+				eeprom: at25@0 {
+					compatible = "atmel,at25";
+				};
+			};
+		};
+
+		fab {
+			tsc@40048000 {
+				status = "okay";
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+		};
+
+		led1 {
+			gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
+			linux,default-trigger = "timer";
+			default-state = "off";
+		};
+	};
+};