diff options
| author | David Woodhouse <David.Woodhouse@intel.com> | 2012-11-21 10:38:13 +0000 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-11-21 10:38:13 +0000 |
| commit | 851462444d421c223965b12b836bef63da61b57f (patch) | |
| tree | 495baa14e638817941496c36e1443aed7dae0ea0 /arch/arm/include/asm/assembler.h | |
| parent | 5a6ea4af0907f995dc06df21a9c9ef764c7cd3bc (diff) | |
| parent | 6924d99fcdf1a688538a3cdebd1f135c22eec191 (diff) | |
Merge branch 'for-3.7' of git://git.infradead.org/users/dedekind/l2-mtd
Conflicts:
drivers/mtd/nand/nand_base.c
Diffstat (limited to 'arch/arm/include/asm/assembler.h')
| -rw-r--r-- | arch/arm/include/asm/assembler.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 5c8b3bf4d82..2ef95813fce 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -22,6 +22,7 @@ #include <asm/ptrace.h> #include <asm/domain.h> +#include <asm/opcodes-virt.h> #define IOMEM(x) (x) @@ -240,6 +241,34 @@ #endif /* + * Helper macro to enter SVC mode cleanly and mask interrupts. reg is + * a scratch register for the macro to overwrite. + * + * This macro is intended for forcing the CPU into SVC mode at boot time. + * you cannot return to the original mode. + * + * Beware, it also clobers LR. + */ +.macro safe_svcmode_maskall reg:req + mrs \reg , cpsr + mov lr , \reg + and lr , lr , #MODE_MASK + cmp lr , #HYP_MODE + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT + bic \reg , \reg , #MODE_MASK + orr \reg , \reg , #SVC_MODE +THUMB( orr \reg , \reg , #PSR_T_BIT ) + bne 1f + orr \reg, \reg, #PSR_A_BIT + adr lr, BSYM(2f) + msr spsr_cxsf, \reg + __MSR_ELR_HYP(14) + __ERET +1: msr cpsr_c, \reg +2: +.endm + +/* * STRT/LDRT access macros with ARM and Thumb-2 variants */ #ifdef CONFIG_THUMB2_KERNEL |