diff options
| author | Len Brown <len.brown@intel.com> | 2010-08-15 01:06:31 -0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2010-08-15 01:06:31 -0400 |
| commit | 95ee46aa8698f2000647dfb362400fadbb5807cf (patch) | |
| tree | e5a05c7297f997e191c73091934e42e3195c0e40 /arch/arm/include/asm/cache.h | |
| parent | cfa806f059801dbe7e435745eb2e187c8bfe1e7f (diff) | |
| parent | 92fa5bd9a946b6e7aab6764e7312e4e3d9bed295 (diff) | |
Merge branch 'linus' into release
Conflicts:
drivers/acpi/debug.c
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 66c160b8547..9d6122096fb 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -14,7 +14,7 @@ * cache before the transfer is done, causing old data to be seen by * the CPU. */ -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES /* * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. |