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| author | Paul Mundt <lethal@linux-sh.org> | 2009-06-11 09:01:14 +0300 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-06-11 09:01:14 +0300 |
| commit | cf9fe114e3b37e14fc8434d5abb192e35df551b1 (patch) | |
| tree | 0f82879295dc792f9df1a3ce79e143a3c073510f /arch/arm/include/asm/cache.h | |
| parent | c1d0d32a603ed06377f404adf2c538de33bb3634 (diff) | |
| parent | 991ec02cdca33b03a132a0cacfe6f0aa0be9aa8d (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index cb7a9e97fd7..feaa75f0013 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -7,4 +7,20 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +/* + * Memory returned by kmalloc() may be used for DMA, so we must make + * sure that all such allocations are cache aligned. Otherwise, + * unrelated code may cause parts of the buffer to be read into the + * cache before the transfer is done, causing old data to be seen by + * the CPU. + */ +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES + +/* + * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. + */ +#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) +#define ARCH_SLAB_MINALIGN 8 +#endif + #endif |