diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-04-25 16:44:23 +0000 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-02 16:21:47 +0000 |
commit | 878040ef831a12855af26a42cc25c817f4fb3f2d (patch) | |
tree | 929921b3d26e7109fdee8b17720d39fc4885b30c /arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h | |
parent | 8a3fb8607a48ed74db3aaa87d8af7febcaa5d814 (diff) |
ARM: bcmring: use proper MMIO accessors
A lot of code in bcmring just dereferences pointers to MMIO
locations, which is not safe. This annotates the pointers
correctly using __iomem and uses readl/write to access them.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h')
-rw-r--r-- | arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index 49403d5725e..f59db25b563 100644 --- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -37,9 +37,9 @@ #define INTCHW_NUM_INTC 3 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) -#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) -#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) +#define INTCHW_INTC0 (MM_IO_BASE_INTC0) +#define INTCHW_INTC1 (MM_IO_BASE_INTC1) +#define INTCHW_SINTC (MM_IO_BASE_SINTC) /* INTC0 - interrupt controller 0 */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ @@ -232,15 +232,15 @@ /* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Function Prototypes --------------------------------------- */ /* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void *basep, uint32_t mask) +static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENCLEAR) = mask; + writel(mask, basep + INTCHW_INTENCLEAR); } /* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void *basep, uint32_t mask) +static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask) { - __REG32(basep + INTCHW_INTENABLE) = mask; + writel(mask, basep + INTCHW_INTENABLE); } #endif /* _INTCHW_REG_H */ |