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authorAnson Huang <b20788@freescale.com>2013-03-21 10:58:06 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-04-12 19:01:43 +0800
commit263475d4e0b0623fb7a22f8ac0a5c01017eabf20 (patch)
tree9d8ffb5e1df3cf19d0b7881e514f585d6387b546 /arch/arm/mach-imx/common.h
parente7b82d645d8b0345508d4b7be85e10f961fbfa3e (diff)
ARM: imx: enable RBC to support anatop LPM mode
RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/common.h')
-rw-r--r--arch/arm/mach-imx/common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index d557bf38328..bcb11b1751d 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -128,6 +128,8 @@ extern void imx_src_prepare_restart(void);
extern void imx_gpc_init(void);
extern void imx_gpc_pre_suspend(void);
extern void imx_gpc_post_resume(void);
+extern void imx_gpc_mask_all(void);
+extern void imx_gpc_restore_all(void);
extern void imx_anatop_init(void);
extern void imx_anatop_pre_suspend(void);
extern void imx_anatop_post_resume(void);