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authorShawn Guo <shawn.guo@linaro.org>2014-11-23 15:07:02 +0800
committerShawn Guo <shawn.guo@linaro.org>2014-11-23 15:07:02 +0800
commit2ce34b105c79ee0404b3a8f68c9ab2ce197dd06f (patch)
tree2111f40b612ccf19b0acb480f82c1e7a80d2e24a /arch/arm/mach-imx/common.h
parent0df1f2487d2f0d04703f142813d53615d62a1da4 (diff)
parent3db47dc0ae4d370ec3c86fc357608132ca695c27 (diff)
Merge tag 'imx-soc-3.19' into imx/dt
The i.MX SoC update for 3.19: - Update i.MX6 suspend code to check DDR instead of CPU type, as the difference we need to handle is between LPDDR2 and DDR3, not SoCs. - Set anatop properly for LPDDR2 in DSM mode - Add support for new SoC LS1021A which integrates dual Cortex-A7 - Add ENET initialization for i.MX6SX platform - Add cpufreq support for i.MX53 platform - Add a SNVS based poweroff driver for i.MX6 platforms - Use ARM Global Timer as clocksource on VF610 Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve a conflict on file arch/arm/mach-imx/clk-vf610.c.
Diffstat (limited to 'arch/arm/mach-imx/common.h')
-rw-r--r--arch/arm/mach-imx/common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 1dabf435c59..fe9a908da3e 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -116,6 +116,7 @@ void imx_anatop_post_resume(void);
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6q_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
+int imx_mmdc_get_ddr_type(void);
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
@@ -157,5 +158,6 @@ static inline void imx_init_l2cache(void) {}
#endif
extern struct smp_operations imx_smp_ops;
+extern struct smp_operations ls1021a_smp_ops;
#endif