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| author | David S. Miller <davem@davemloft.net> | 2011-04-11 13:44:25 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-04-11 13:44:25 -0700 |
| commit | 1c01a80cfec6f806246f31ff2680cd3639b30e67 (patch) | |
| tree | 0b554aad2ec1da71ecf6339d4ba51617bfe1dc3c /arch/arm/mach-lpc32xx/pm.c | |
| parent | c44d79950b2daa1025e62eede73e4e4a274d1ef3 (diff) | |
| parent | 4a9f65f6304a00f6473e83b19c1e83caa1e42530 (diff) | |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
drivers/net/smsc911x.c
Diffstat (limited to 'arch/arm/mach-lpc32xx/pm.c')
| -rw-r--r-- | arch/arm/mach-lpc32xx/pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c index e76d41bb705..b9c80597b7b 100644 --- a/arch/arm/mach-lpc32xx/pm.c +++ b/arch/arm/mach-lpc32xx/pm.c @@ -41,7 +41,7 @@ * DRAM clocking and refresh are slightly different for systems with DDR * DRAM or regular SDRAM devices. If SDRAM is used in the system, the * SDRAM will still be accessible in direct-run mode. In DDR based systems, - * a transistion to direct-run mode will stop all DDR accesses (no clocks). + * a transition to direct-run mode will stop all DDR accesses (no clocks). * Because of this, the code to switch power modes and the code to enter * and exit DRAM self-refresh modes must not be executed in DRAM. A small * section of IRAM is used instead for this. |