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authorAbhijeet Dharmapurikar <adharmap@codeaurora.org>2010-02-01 12:30:28 -0800
committerDaniel Walker <dwalker@codeaurora.org>2010-10-08 15:12:45 -0700
commite4fbb68f4594388367e4e4595abf9330d9875704 (patch)
tree27fceae10c83138846c54bf2bf78345f89cc492f /arch/arm/mach-msm
parent569fb6e3e60eef77941c319562271daf759e634d (diff)
msm: 8x60: setup correct handlers for private interrupts
Private Peripheral interrupts could be edge triggered or level triggered depending on the platform. Initialize handlers for these in board file. Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index e7feb99b5cf..70087cad673 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -44,7 +44,7 @@ static void __init msm8x60_init_irq(void)
{
unsigned int i;
- gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
+ gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);