Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull "ARM: More SoC support updates" from Olof Johansson:
 "This branch contains a handful of updates of SoC base code that had
  dependencies on other external trees that have now been merged:

   * Support for the new EXYNOS5250 SoC from Samsung
   * SMP and power domain support for Tegra3 from NVIDIA
   * ux500 updates for exporting SoC information through sysfs"

Fix up trivial merge conflicts as per Olof.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits)
  ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer
  ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board
  ARM: dts: add initial dts file for EXYNOS5250, SMDK5250
  ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
  ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
  ARM: EXYNOS: add support get_core_count() for EXYNOS5250
  ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
  ARM: EXYNOS: add interrupt definitions for EXYNOS5250
  ARM: EXYNOS: add support for EXYNOS5250 SoC
  ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
  ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
  ARM: EXYNOS: add clock part for EXYNOS5250 SoC
  ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
  ARM: EXYNOS: to declare static for mach-exynos/common.c
  ARM: EXYNOS: Add clkdev lookup entry for lcd clock
  ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
  ARM: tegra: support for secondary cores on Tegra30
  ARM: tegra: support for Tegra30 CPU powerdomains
  ARM: tegra: add support for Tegra30 powerdomains
  ARM: tegra: export tegra_powergate_is_powered()
  ...

1 files changed, 84 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
new file mode 100644
index 00000000000..4d6a2ee99c3
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-tegra/reset.c
+ *
+ * Copyright (C) 2011,2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/bitops.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/iomap.h>
+#include <mach/irammap.h>
+
+#include "reset.h"
+#include "fuse.h"
+
+#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
+				TEGRA_IRAM_RESET_HANDLER_OFFSET)
+
+static bool is_enabled;
+
+static void tegra_cpu_reset_handler_enable(void)
+{
+	void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
+	void __iomem *evp_cpu_reset =
+		IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
+	void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
+	u32 reg;
+
+	BUG_ON(is_enabled);
+	BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
+
+	memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
+			tegra_cpu_reset_handler_size);
+
+	/*
+	 * NOTE: This must be the one and only write to the EVP CPU reset
+	 *       vector in the entire system.
+	 */
+	writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
+			evp_cpu_reset);
+	wmb();
+	reg = readl(evp_cpu_reset);
+
+	/*
+	 * Prevent further modifications to the physical reset vector.
+	 *  NOTE: Has no effect on chips prior to Tegra30.
+	 */
+	if (tegra_chip_id != TEGRA20) {
+		reg = readl(sb_ctrl);
+		reg |= 2;
+		writel(reg, sb_ctrl);
+		wmb();
+	}
+
+	is_enabled = true;
+}
+
+void __init tegra_cpu_reset_handler_init(void)
+{
+
+#ifdef CONFIG_SMP
+	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
+		*((u32 *)cpu_present_mask);
+	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
+		virt_to_phys((void *)tegra_secondary_startup);
+#endif
+
+	tegra_cpu_reset_handler_enable();
+}