diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2010-09-13 15:58:37 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-09-19 12:17:45 +0100 |
| commit | 85848dd7ab75fce1134856228582a8df522c91d9 (patch) | |
| tree | 3b5f34bf871e983d30fad787c098e6d778d962bd /arch/arm/mm/cache-tauros2.c | |
| parent | 6012191aa9c6ffff3a23b81162298318b56d7cb3 (diff) | |
ARM: 6381/1: Use lazy cache flushing on ARMv7 SMP systems
ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.
Note that cache flushing on SMP systems now takes place via the
set_pte_at() call (__sync_icache_dcache) and there is no race with other
CPUs executing code from the new PTE before the cache flushing took
place.
Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-tauros2.c')
0 files changed, 0 insertions, 0 deletions