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| author | Kevin Hilman <khilman@ti.com> | 2012-03-05 15:37:04 -0800 |
|---|---|---|
| committer | Kevin Hilman <khilman@ti.com> | 2012-03-05 15:37:04 -0800 |
| commit | 015f1e4297ad32f83251f3f4cee2389ce5516e9e (patch) | |
| tree | 1b16e317005dc3d09b0551a4db9182f7f4119f71 /arch/arm/mm/cache-v7.S | |
| parent | 1b35af54ee9cbbdd13fed53fd4acb0952ba522e1 (diff) | |
| parent | 9cf793f9b8b1ba9414e2a7591b2e911885f85a27 (diff) | |
Merge remote-tracking branch 'omap/hsmmc' into for_3.4/cleanup/pm-base
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 07c4bc8ea0a..7a24d39661f 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -54,9 +54,15 @@ loop1: and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache +#ifdef CONFIG_PREEMPT + save_and_disable_irqs r9 @ make cssr&csidr read atomic +#endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr +#ifdef CONFIG_PREEMPT + restore_irqs_notrace r9 +#endif and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff |