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author | Grant Likely <grant.likely@secretlab.ca> | 2010-01-28 14:38:25 -0700 |
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committer | Grant Likely <grant.likely@secretlab.ca> | 2010-01-28 14:38:25 -0700 |
commit | 0ada0a73120c28cc432bcdbac061781465c2f48f (patch) | |
tree | d17cadd4ea47e25d9e48e7d409a39c84268fbd27 /arch/arm/mm/cache-xsc3l2.c | |
parent | 6016a363f6b56b46b24655bcfc0499b715851cf3 (diff) | |
parent | 92dcffb916d309aa01778bf8963a6932e4014d07 (diff) |
Merge commit 'v2.6.33-rc5' into secretlab/test-devicetree
Diffstat (limited to 'arch/arm/mm/cache-xsc3l2.c')
-rw-r--r-- | arch/arm/mm/cache-xsc3l2.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 5d180cb0bd9..c3154928bcc 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c @@ -221,15 +221,14 @@ static int __init xsc3_l2_init(void) if (!cpu_is_xsc3() || !xsc3_l2_present()) return 0; - if (!(get_cr() & CR_L2)) { + if (get_cr() & CR_L2) { pr_info("XScale3 L2 cache enabled.\n"); - adjust_cr(CR_L2, CR_L2); xsc3_l2_inv_all(); - } - outer_cache.inv_range = xsc3_l2_inv_range; - outer_cache.clean_range = xsc3_l2_clean_range; - outer_cache.flush_range = xsc3_l2_flush_range; + outer_cache.inv_range = xsc3_l2_inv_range; + outer_cache.clean_range = xsc3_l2_clean_range; + outer_cache.flush_range = xsc3_l2_flush_range; + } return 0; } |