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authorLinus Torvalds <torvalds@linux-foundation.org>2012-09-13 09:05:22 +0800
committerLinus Torvalds <torvalds@linux-foundation.org>2012-09-13 09:05:22 +0800
commit8507876aaada8a2cf68ebccdf1d056465dd1fc11 (patch)
treeae8a028afcf5131dcf99d2fb31564524f05507e4 /arch/arm/mm/context.c
parent22b4e63ebe062e2e3d4a3a2b468e47ca9575d598 (diff)
parentbeafa0de3d3e0d0ece7638cded879815f359f1cb (diff)
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King: "It's been a while... so there's a little more here than normal. Mostly updates from Will for the breakpoint stuff, and plugging a few holes in the user access functions which crept in when domain support was disabled for ARMv7 CPUs." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7529/1: delay: set loops_per_jiffy when moving to timer-based loop ARM: 7528/1: uaccess: annotate [__]{get,put}_user functions with might_fault() ARM: 7527/1: uaccess: explicitly check __user pointer when !CPU_USE_DOMAINS ARM: 7526/1: traps: send SIGILL if get_user fails on undef handling path ARM: 7521/1: Fix semihosting Kconfig text ARM: 7513/1: Make sure dtc is built before running it ARM: 7512/1: Fix XIP build due to PHYS_OFFSET definition moving ARM: 7499/1: mm: Fix vmalloc overlap check for !HIGHMEM ARM: 7503/1: mm: only flush both pmd entries for classic MMU ARM: 7502/1: contextidr: avoid using bfi instruction during notifier ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores ARM: 7497/1: hw_breakpoint: allow single-byte watchpoints on all addresses ARM: 7496/1: hw_breakpoint: don't rely on dfsr to show watchpoint access type ARM: Fix ioremap() of address zero
Diffstat (limited to 'arch/arm/mm/context.c')
-rw-r--r--arch/arm/mm/context.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 119bc52ab93..4e07eec1270 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -63,10 +63,11 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
pid = task_pid_nr(thread->task) << ASID_BITS;
asm volatile(
" mrc p15, 0, %0, c13, c0, 1\n"
- " bfi %1, %0, #0, %2\n"
- " mcr p15, 0, %1, c13, c0, 1\n"
+ " and %0, %0, %2\n"
+ " orr %0, %0, %1\n"
+ " mcr p15, 0, %0, c13, c0, 1\n"
: "=r" (contextidr), "+r" (pid)
- : "I" (ASID_BITS));
+ : "I" (~ASID_MASK));
isb();
return NOTIFY_OK;