diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 21:37:51 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 21:37:51 +0200 |
| commit | 602b9ba2cb0c62595fa94650f9826ee37f6c633c (patch) | |
| tree | aa7dce9b8b603177daf93cd58e28a6e34acfe26f /arch/arm/mm/proc-mohawk.S | |
| parent | 853b20396becfe9425f4d5da74e10ea67811b188 (diff) | |
| parent | 902ca2297180fe97f840427c114cc6dc7e77375e (diff) | |
Merge branch 'power' of git://github.com/hzhuang1/linux into next/pm
* 'power' of git://github.com/hzhuang1/linux:
ARM: mmp: add pm support for pxa910
ARM: mmp: ttc_dkb: add PMIC support
ARM: cache: tauros2: add disable and resume callback
ARM: mm: proc-mohawk: add suspend resume for mohawk
ARM: mmp: add PM support for mmp2
ARM: mmp: move XX_REG definition to addr-map.h
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mm/proc-mohawk.S')
| -rw-r--r-- | arch/arm/mm/proc-mohawk.S | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index cdfedc5b8ad..6a050b19cdf 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -344,6 +344,41 @@ ENTRY(cpu_mohawk_set_pte_ext) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr +.globl cpu_mohawk_suspend_size +.equ cpu_mohawk_suspend_size, 4 * 6 +#ifdef CONFIG_PM_SLEEP +ENTRY(cpu_mohawk_do_suspend) + stmfd sp!, {r4 - r9, lr} + mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode + mrc p15, 0, r5, c15, c1, 0 @ CP access reg + mrc p15, 0, r6, c13, c0, 0 @ PID + mrc p15, 0, r7, c3, c0, 0 @ domain ID + mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg + mrc p15, 0, r9, c1, c0, 0 @ control reg + bic r4, r4, #2 @ clear frequency change bit + stmia r0, {r4 - r9} @ store cp regs + ldmia sp!, {r4 - r9, pc} +ENDPROC(cpu_mohawk_do_suspend) + +ENTRY(cpu_mohawk_do_resume) + ldmia r0, {r4 - r9} @ load cp regs + mov ip, #0 + mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB + mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer + mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. + mcr p15, 0, r5, c15, c1, 0 @ CP access reg + mcr p15, 0, r6, c13, c0, 0 @ PID + mcr p15, 0, r7, c3, c0, 0 @ domain ID + orr r1, r1, #0x18 @ cache the page table in L2 + mcr p15, 0, r1, c2, c0, 0 @ translation table base addr + mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg + mov r0, r9 @ control register + b cpu_resume_mmu +ENDPROC(cpu_mohawk_do_resume) +#endif + __CPUINIT .type __mohawk_setup, #function |