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| author | Linus Walleij <linus.walleij@linaro.org> | 2013-04-03 22:18:36 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-04-03 22:18:36 +0200 |
| commit | 6a7b3e970426f4bc2a8d52f81a4fda6595a9f052 (patch) | |
| tree | 055765564c839e456fbe4c65c8cd2c4b00d731b7 /arch/arm/plat-orion | |
| parent | 661462f4c6d3c9ae0bac193c65936ebfac4c95b4 (diff) | |
| parent | 07961ac7c0ee8b546658717034fe692fd12eefa9 (diff) | |
Merge tag 'v3.9-rc5' into devel
Linux 3.9-rc5
Conflicts:
drivers/pinctrl/pinconf.c
Diffstat (limited to 'arch/arm/plat-orion')
| -rw-r--r-- | arch/arm/plat-orion/addr-map.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index febe3862873..807ac8e5cbc 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -157,9 +157,12 @@ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); /* - * Chip select enabled? + * We only take care of entries for which the chip + * select is enabled, and that don't have high base + * address bits set (devices can only access the first + * 32 bits of the memory). */ - if (size & 1) { + if ((size & 1) && !(base & 0xF)) { struct mbus_dram_window *w; w = &orion_mbus_dram_info.cs[cs++]; |