diff options
| author | Eric Miao <eric.miao@marvell.com> | 2008-09-08 15:37:50 +0800 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-07 19:12:56 +0100 |
| commit | 52358ba3a89012c54712c24074ceb4b1c669af52 (patch) | |
| tree | 856804ad95548a3e1dcf577366308cf0ebcc1369 /arch/arm | |
| parent | 87f3dd77974cba1ba0798abd741ede50f56b3eb3 (diff) | |
[ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/pxa-regs.h | 39 |
1 files changed, 1 insertions, 38 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index 4cac9269fdf..98ded450d0f 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -269,46 +269,9 @@ */ /* - * Serial Audio Controller + * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c */ -#define SACR0 __REG(0x40400000) /* Global Control Register */ -#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ -#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ -#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ -#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ -#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ -#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ - -#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ -#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ -#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ -#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ -#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ -#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ -#define SACR0_ENB (1 << 0) /* Enable I2S Link */ -#define SACR1_ENLBF (1 << 5) /* Enable Loopback */ -#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ -#define SACR1_DREC (1 << 3) /* Disable Recording Function */ -#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ - -#define SASR0_I2SOFF (1 << 7) /* Controller Status */ -#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ -#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ -#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ -#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ -#define SASR0_BSY (1 << 2) /* I2S Busy */ -#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ -#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ - -#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ -#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ - -#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ -#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ -#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ -#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ - /* * AC97 Controller registers */ |