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authorYi Li <yi.li@analog.com>2009-08-05 10:02:14 +0000
committerMike Frysinger <vapier@gentoo.org>2009-09-16 22:10:16 -0400
commitbd411b15cc4b3f31f67d15e1afffbd1ec650d5b8 (patch)
tree658a99ef56dbd2c20a7a46a00c181f87059bb753 /arch/blackfin/mach-bf561/include/mach
parentf1cb64625c4f5309747b8067a309e0bcc630b303 (diff)
Blackfin: update anomaly lists
Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index a5312b2d267..70da495c966 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -262,6 +262,8 @@
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */