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| author | Felix Blyakher <felixb@sgi.com> | 2009-02-09 09:34:45 -0600 |
|---|---|---|
| committer | Felix Blyakher <felixb@sgi.com> | 2009-02-09 09:34:45 -0600 |
| commit | d41d4113f49e16bfab02eff0248282200be21807 (patch) | |
| tree | ae84803c22a09f138023ef62de73712f324bc62d /arch/blackfin/mach-common/clocks-init.c | |
| parent | b58a4cc51f4f569c6a86979890f9b237a504ab6b (diff) | |
| parent | d5b562330ec766292a3ac54ae5e0673610bd5b3d (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/blackfin/mach-common/clocks-init.c')
| -rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 5d182abefc7..9dddb6f8cc8 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c @@ -14,6 +14,7 @@ #include <asm/clocks.h> #include <asm/mem_init.h> +#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define PLL_CTL_VAL \ (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) @@ -76,7 +77,7 @@ void init_clocks(void) bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); #ifdef EBIU_SDGCTL bfin_write_EBIU_SDRRC(mem_SDRRC); - bfin_write_EBIU_SDGCTL(mem_SDGCTL); + bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); #else bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); do_sync(); |