diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2007-11-21 23:49:52 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2007-11-21 23:49:52 +0800 |
| commit | e40540b304d5d15c344585c4a7b3116e73add2db (patch) | |
| tree | e991ef8446686a84640f77f76c2f88d89e68b8ff /arch/blackfin | |
| parent | 28a44d4bd6bdc7d013405bfc2aa7f126d39a7b2b (diff) | |
Blackfin arch: fix bug NOR Flash MTD mount fail
Config EBIU flash mode properly. EBIU_MODE EBIU_FCTL
EBIU_MBSCTL register should be configurd to Flash
mode.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/Kconfig | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf548/head.S | 21 |
2 files changed, 35 insertions, 0 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 2e5ce848513..3bb25da8b50 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -866,6 +866,20 @@ config BANK_3 default 0x99B3 endmenu +config EBIU_MBSCTLVAL + hex "EBIU Bank Select Control Register" + depends on BF54x + default 0 + +config EBIU_MODEVAL + hex "Flash Memory Mode Control Register" + depends on BF54x + default 1 + +config EBIU_FCTLVAL + hex "Flash Memory Bank Control Register" + depends on BF54x + default 6 endmenu ############################################################################# diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 3071c243d42..74b34c7f362 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S @@ -158,6 +158,27 @@ ENTRY(__stext) w[p2] = r0; ssync; + p2.h = hi(EBIU_MBSCTL); + p2.l = lo(EBIU_MBSCTL); + r0.h = hi(CONFIG_EBIU_MBSCTLVAL); + r0.l = lo(CONFIG_EBIU_MBSCTLVAL); + [p2] = r0; + ssync; + + p2.h = hi(EBIU_MODE); + p2.l = lo(EBIU_MODE); + r0.h = hi(CONFIG_EBIU_MODEVAL); + r0.l = lo(CONFIG_EBIU_MODEVAL); + [p2] = r0; + ssync; + + p2.h = hi(EBIU_FCTL); + p2.l = lo(EBIU_FCTL); + r0.h = hi(CONFIG_EBIU_FCTLVAL); + r0.l = lo(CONFIG_EBIU_FCTLVAL); + [p2] = r0; + ssync; + /* This section keeps the processor in supervisor mode * during kernel boot. Switches to user mode at end of boot. * See page 3-9 of Hardware Reference manual for documentation. |