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authorIngo Molnar <mingo@elte.hu>2008-08-11 13:40:56 +0200
committerIngo Molnar <mingo@elte.hu>2008-08-11 13:40:56 +0200
commit251a169c69d1ff07cee7a9bb9fc4faff6b1d2ac3 (patch)
tree3c20c3e080f276848f2ad67aadab44a5d64bfda9 /arch/ia64/include/asm/sn/rw_mmr.h
parent6679ce6e5f519096612b480d255d9ca97be0c2be (diff)
parent796aadeb1b2db9b5d463946766c5bbfd7717158c (diff)
Merge branch 'linus' into sched/urgent
Diffstat (limited to 'arch/ia64/include/asm/sn/rw_mmr.h')
-rw-r--r--arch/ia64/include/asm/sn/rw_mmr.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/ia64/include/asm/sn/rw_mmr.h b/arch/ia64/include/asm/sn/rw_mmr.h
new file mode 100644
index 00000000000..2d78f4c5a45
--- /dev/null
+++ b/arch/ia64/include/asm/sn/rw_mmr.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
+ */
+#ifndef _ASM_IA64_SN_RW_MMR_H
+#define _ASM_IA64_SN_RW_MMR_H
+
+
+/*
+ * This file that access MMRs via uncached physical addresses.
+ * pio_phys_read_mmr - read an MMR
+ * pio_phys_write_mmr - write an MMR
+ * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
+ * Second MMR will be skipped if address is NULL
+ *
+ * Addresses passed to these routines should be uncached physical addresses
+ * ie., 0x80000....
+ */
+
+
+extern long pio_phys_read_mmr(volatile long *mmr);
+extern void pio_phys_write_mmr(volatile long *mmr, long val);
+extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
+
+#endif /* _ASM_IA64_SN_RW_MMR_H */