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authorGreg Ungerer <gerg@uclinux.org>2011-12-24 12:36:38 +1000
committerGreg Ungerer <gerg@uclinux.org>2012-03-05 09:43:09 +1000
commit36d175a4b249235927d75fb681484bd97cc4ea41 (patch)
tree9e2733c046d7299564c06be048505cc12565aea6 /arch/m68k/include/asm/m523xsim.h
parenta4e2e2ac08f73dedeabecb9e1141a05889591b7b (diff)
m68knommu: make 523x QSPI platform addressing consistent
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 523x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m523xsim.h')
-rw-r--r--arch/m68k/include/asm/m523xsim.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index e1988dd372f..f2d21cef094 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -51,6 +51,8 @@
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
+#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
+
/*
* SDRAM configuration registers.
*/
@@ -83,6 +85,17 @@
#define MCFFEC_SIZE0 0x800
/*
+ * QSPI module.
+ */
+#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE 0x40
+
+#define MCFQSPI_CS0 91
+#define MCFQSPI_CS1 92
+#define MCFQSPI_CS2 103
+#define MCFQSPI_CS3 99
+
+/*
* GPIO module.
*/
#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)