diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-04 13:53:26 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:18 +1000 |
| commit | 1c83af5f9d7e15a091f11394ad5916a7dcf1a99e (patch) | |
| tree | aa41743fb552319bb53959a7df228233d4f04ba2 /arch/m68k/include/asm/m54xxacr.h | |
| parent | 0762346034a3e94f9c3a5fe8d7c4bcaffbc1cd53 (diff) | |
m68knommu: use user stack pointer hardware on some ColdFire cores
The more modern ColdFire parts (even if based on older version cores)
have separate user and supervisor stack pointers (a7 register).
Modify the ColdFire CPU setup and exception code to enable and use
this on parts that have it.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m54xxacr.h')
| -rw-r--r-- | arch/m68k/include/asm/m54xxacr.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 76d64906aa6..12209c68b90 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -26,6 +26,7 @@ #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ +#define CACR_EUSP 0x00000020 /* Enable separate user a7 */ #define ACR_BASE_POS 24 /* Address Base */ #define ACR_MASK_POS 16 /* Address Mask */ @@ -67,7 +68,11 @@ /* Enable data store buffer */ /* outside ACRs : No cache, precise */ /* Enable instruction+branch caches */ +#if defined(CONFIG_M5407) #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC) +#else +#define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) +#endif #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) |