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authorKelvin Cheung <keguang.zhang@gmail.com>2014-10-10 11:40:01 +0800
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 07:45:09 +0100
commitf29ad10de6c345c8ae4cb33a99ba8ff29bdcd751 (patch)
treeac377224cfbe7b116ad9f68deb85fd9dc84f93c4 /arch/mips/Kconfig
parent813c14108d0f5bbddc125fb7a6a0819fcdcf61e2 (diff)
MIPS: Loongson1B: Some fixes/updates for LS1B
- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data. (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1) - Add GMAC1 support and setup MUX in terms of PHY mode. - Add CPUFreq support. - Add MUX Register Definitions. - Add PWM Register Definitions. - Update clock register bitfields according to the latest spec. - Update clock related stuff. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
-rw-r--r--arch/mips/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4a7e0c13c61..9ea76ed1c2e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1573,6 +1573,7 @@ config CPU_LOONGSON1
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
+ select CPU_SUPPORTS_CPUFREQ
config CPU_BMIPS32_3300
select SMP_UP if SMP