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authorWu Zhangjin <wuzhangjin@gmail.com>2010-04-13 13:16:34 +0800
committerRalf Baechle <ralf@linux-mips.org>2010-05-21 21:31:14 +0100
commitb8853aa3d912f47f649ad8de784ac3afd932437d (patch)
tree02939e404694eb0067b149d54c6191fea04de68f /arch/mips/alchemy/devboards/pb1550
parented1bbdefc39477a1301fb466139ffb0c00f0d006 (diff)
MIPS: Loongson: update cpu-feature-overrides.h
Loongson doesn't support MIPSR2, therefore, MIPSR2 vectored interrupts (cpu_has_vint) and MIPSR2 external interrupt controller mode (cpu_has_veic) are 0. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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