diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
| commit | 0d4a42f6bd298e826620585e766a154ab460617a (patch) | |
| tree | 406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/mips/include/asm/asm.h | |
| parent | d62b4892f3d9f7dd2002e5309be10719d6805b0f (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes,
which depend upon the new for_each_sg_page introduce in
commit a321e91b6d73ed011ffceed384c40d2785cf723b
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Feb 27 17:02:56 2013 -0800
lib/scatterlist: add simple page iterator
The merge itself is just two trivial conflicts:
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/mips/include/asm/asm.h')
| -rw-r--r-- | arch/mips/include/asm/asm.h | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h index 608cfcfbb3e..164a21e65b4 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -33,12 +33,12 @@ * Not used for the kernel but here seems to be the right place. */ #ifdef __PIC__ -#define CPRESTORE(register) \ +#define CPRESTORE(register) \ .cprestore register -#define CPADD(register) \ +#define CPADD(register) \ .cpadd register -#define CPLOAD(register) \ - .cpload register +#define CPLOAD(register) \ + .cpload register #else #define CPRESTORE(register) #define CPADD(register) @@ -48,35 +48,35 @@ /* * LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, 0, ra /* * NESTED - declare nested routine entry point */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol, @function; \ + .ent symbol, 0; \ symbol: .frame sp, framesize, rpc /* * END - mark end of function */ -#define END(function) \ - .end function; \ +#define END(function) \ + .end function; \ .size function, .-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* @@ -90,16 +90,16 @@ symbol: /* * ABS - export absolute symbol */ -#define ABS(symbol,value) \ - .globl symbol; \ +#define ABS(symbol,value) \ + .globl symbol; \ symbol = value -#define PANIC(msg) \ +#define PANIC(msg) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal panic; \ -9: b 9b; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal panic; \ +9: b 9b; \ .set pop; \ TEXT(msg) @@ -107,31 +107,31 @@ symbol = value * Print formatted string */ #ifdef CONFIG_PRINTK -#define PRINT(string) \ +#define PRINT(string) \ .set push; \ - .set reorder; \ - PTR_LA a0, 8f; \ - jal printk; \ + .set reorder; \ + PTR_LA a0, 8f; \ + jal printk; \ .set pop; \ TEXT(string) #else #define PRINT(string) #endif -#define TEXT(msg) \ +#define TEXT(msg) \ .pushsection .data; \ -8: .asciiz msg; \ +8: .asciiz msg; \ .popsection; /* * Build text tables */ -#define TTABLE(string) \ +#define TTABLE(string) \ .pushsection .text; \ - .word 1f; \ + .word 1f; \ .popsection \ .pushsection .data; \ -1: .asciiz string; \ +1: .asciiz string; \ .popsection /* @@ -143,13 +143,13 @@ symbol = value */ #ifdef CONFIG_CPU_HAS_PREFETCH -#define PREF(hint,addr) \ +#define PREF(hint,addr) \ .set push; \ .set mips4; \ pref hint, addr; \ .set pop -#define PREFX(hint,addr) \ +#define PREFX(hint,addr) \ .set push; \ .set mips4; \ prefx hint, addr; \ @@ -166,42 +166,42 @@ symbol = value * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs. */ #if (_MIPS_ISA == _MIPS_ISA_MIPS1) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set reorder; \ - beqz rt, 9f; \ - move rd, rs; \ + beqz rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set reorder; \ - bnez rt, 9f; \ - move rd, rs; \ + bnez rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */ #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ .set push; \ .set noreorder; \ - bnezl rt, 9f; \ - move rd, rs; \ + bnezl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ .set push; \ .set noreorder; \ - beqzl rt, 9f; \ - move rd, rs; \ + beqzl rt, 9f; \ + move rd, rs; \ .set pop; \ 9: #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */ #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \ (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64) -#define MOVN(rd, rs, rt) \ +#define MOVN(rd, rs, rt) \ movn rd, rs, rt -#define MOVZ(rd, rs, rt) \ +#define MOVZ(rd, rs, rt) \ movz rd, rs, rt #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */ |