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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2014-07-24 12:36:56 -0700 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2014-07-24 12:36:56 -0700 |
| commit | b9f12a5d97f652c77ef6803dccd0d40d1290f5be (patch) | |
| tree | 8f58c8620ffef0d350a5ec022feda492a96b179a /arch/mips/include/asm/cpu-features.h | |
| parent | 9d8dc3e529a19e427fd379118acd132520935c5d (diff) | |
| parent | 9a3c4145af32125c5ee39c0272662b47307a8323 (diff) | |
Merge tag 'v3.16-rc6' into next
Merge with mainline to bring in changes to MFD to allow merging
ipaq-micro-ts driver.
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index f56cc975b92..c7d8c997d93 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -110,9 +110,15 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif + #ifndef cpu_has_rixi -#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# ifdef CONFIG_64BIT +# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# else /* CONFIG_32BIT */ +# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits) +# endif #endif + #ifndef cpu_has_mmips # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) @@ -120,6 +126,7 @@ # define cpu_has_mmips 0 # endif #endif + #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif @@ -183,6 +190,17 @@ /* * Shortcuts ... */ +#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) +#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) +#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) + +#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) +#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) +#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) +#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) + +#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2) + #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) |