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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-10-17 09:32:49 -0300
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-10-17 09:32:49 -0300
commit214e2ca2b82d335935a861c253fe94c61ad77aad (patch)
treeeee42ff74d10470789d919b8499737ad0e919360 /arch/mips/include/asm/cpu.h
parent1fdead8ad31d3aa833bc37739273fcde89ace93c (diff)
parentddffeb8c4d0331609ef2581d84de4d763607bd37 (diff)
Merge tag 'v3.7-rc1' into staging/for_v3.8
Linux 3.7-rc1 * tag 'v3.7-rc1': (9579 commits) Linux 3.7-rc1 x86, boot: Explicitly include autoconf.h for hostprogs perf: Fix UAPI fallout ARM: config: make sure that platforms are ordered by option string ARM: config: sort select statements alphanumerically UAPI: (Scripted) Disintegrate include/linux/byteorder UAPI: (Scripted) Disintegrate include/linux UAPI: Unexport linux/blk_types.h UAPI: Unexport part of linux/ppp-comp.h perf: Handle new rbtree implementation procfs: don't need a PATH_MAX allocation to hold a string representation of an int vfs: embed struct filename inside of names_cache allocation if possible audit: make audit_inode take struct filename vfs: make path_openat take a struct filename pointer vfs: turn do_path_lookup into wrapper around struct filename variant audit: allow audit code to satisfy getname requests from its names_list vfs: define struct filename and have getname() return it btrfs: Fix compilation with user namespace support enabled userns: Fix posix_acl_file_xattr_userns gid conversion userns: Properly print bluetooth socket uids ...
Diffstat (limited to 'arch/mips/include/asm/cpu.h')
-rw-r--r--arch/mips/include/asm/cpu.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f21b7c04e95..52c4e914f95 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -94,6 +94,7 @@
#define PRID_IMP_24KE 0x9600
#define PRID_IMP_74K 0x9700
#define PRID_IMP_1004K 0x9900
+#define PRID_IMP_1074K 0x9a00
#define PRID_IMP_M14KC 0x9c00
/*
@@ -319,6 +320,8 @@ enum cpu_type_enum {
#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
+#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
+#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
/*
* CPU ASE encodings
@@ -329,6 +332,7 @@ enum cpu_type_enum {
#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
+#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
#endif /* _ASM_CPU_H */